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AR# 65467

Zynq UltraScale+ MPSoC - Boot and Configuration

Description

This answer record helps you find all Zynq UltraScale+ MPSoC solutions related to boot and configuration known issues.

Note: This answer record is part of Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).

The Xilinx Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to Zynq UltraScale+ MPSoC.

Whether you are starting a new design or troubleshooting a problem, use the Zynq UltraScale+ MPSoC Solution Center to guide you to the right information.

Solution

Find all you need to know about booting a Zynq UltraScale+ MPSoC device

(Xilinx Answer 65468)Zynq UltraScale+ MPSoC - Booting a Zynq UltraScale+ MPSoC Device


Top Xilinx Answer Records on Boot and Configuration

(Xilinx Answer 65463)Zynq UltraScale+ MPSoC - What devices are supported for configuration?
(Xilinx Answer 66740)Zynq UltraScale+ MPSoC - What are the PL configuration bitstream lengths for the Zynq UltraScale+ MPSoC devices?

 

Top Xilinx Answer Records on Debugging Programming/Booting

(Xilinx Answer 68656)Zynq UltraScale+ MPSoC: QSPI Programming/Booting Checklist
(Xilinx Answer 66436)XSDB is not able to connect to PSU after successfully booting in SD mode on a ZCU102 board
(Xilinx Answer 66437)psu_post_config (from psu_init.tcl) sometimes hangs on a ZCU102 board

 

Known issues for VIVADO/XSDK programming flash tools

Xilinx AnswerTitleTool Version FoundTool Version Resolved
(Xilinx Answer 69168)2016.x/2017.1 Zynq UltraScale+ MPSoC - QSPI programming fails for Dual Stacked Configuration2016.12017.3
(Xilinx Answer 68237)2016.x/2017.1 Zynq UltraScale+ MPSoC - QSPI programming requires the QSPI Feedback Clock on MIO6 2016.12017.3
(Xilinx Answer 66715)QSPI programming on an ZCU102 board requires the Zynq UltraScale+ device to boot in JTAG mode 2016.12017.3

Known Configuration related issues for u-boot

Xilinx AnswerTitleTool Version FoundTool Version Resolved
(Xilinx Answer 68831)Zynq UltraScale+ MPSoC: 2016.4 u-boot fails to write ondie-ECC NAND 2016.42017.3
(Xilinx Answer 68476)Zynq UltraScale+ MPSoC - 2016.3 u-boot - cannot probe Spansion QSPI flash in dual parallel mode 2016.32017.1
(Xilinx Answer 68061)2016.3 Zynq UltraScale+ MPSoC, Create Boot Image: u-boot image fails to boot 2016.3N.A.
(Xilinx Answer 68657)  Zynq UltraScale+ MPSoC: How to use u-boot to program a "known to work" QSPI flash?N.A.N.A.
(Xilinx Answer 66438)On ZCU102 QSPI24 warm booting hangs if u-boot was previously executedN.A.N.A.

 

Known issues for XSDK FSBL

Xilinx AnswerTitleTool Version FoundTool Version Resolved
(Xilinx Answer 68732)2017.1 Zynq UltraScale+ MPSoC, Boot Image fails to boot if bitstream is placed after ATF 2017.1N.A.
(Xilinx Answer 69149)2016.4 Zynq UltraScale+ MPSoC: FSBL fails to decrypt bitstream if the image is place in QSPI at a multiple of 32K offset 2106.42017.1
(Xilinx Answer 68582)Zynq UltraScale+ MPSoC: 2016.4 FSBL hang when DDR ECC is enabled2016.42017.1
(Xilinx Answer 68969)Zynq UltraScale+ MPSoC: 2016.x FSBL fails to load an R5 application with SHA3 checksum2016.32017.1
(Xilinx Answer 67953)Zynq UltraScale+ MPSoC, 2016.3 FSBL and PMUFW: Support for Isolation (Enhanced Security Configuration) 2016.3N.A.
(Xilinx Answer 67955)Zynq UltraScale+ MPSoC, 2016.3 FSBL: Adding XFsbl_HookPsuInit() allows you to load alternative psu_init2016.3N.A.
(Xilinx Answer 68166)Zynq UltraScale+ MPSoC - PS-PL AXI widths not configured in 2016.3 FSBL2016.32016.4
(Xilinx Answer 68001)Zynq UltraScale+ MPSoC, 2016.3 FSBL: Vectors region overwritten in R5 with secure partitions.2016.32017.1
(Xilinx Answer 67954)Zynq UltraScale+ MPSoC, 2016.3 FSBL: Memory Layout changes2016.3N.A.
(Xilinx Answer 68211)Zynq UltraScale+ MPSoC -  FSBL does not initialize above first 2GB of PS DDR when using ECC, causing program exceptions 2016.32016.4 2017.1
(Xilinx Answer 67987)Zynq UltraScale+ MPSoC: 2016.3 FSBL and psu_init.tcl TCM ECC Initialization2016.32017.1
(Xilinx Answer 67569)Zynq UltraScale+ MPSoC - 2016.2 FSBL Configuration Performs Degrades When XFSBL_PERF Mode Is Enabled 2016.22016.3
(Xilinx Answer 66295)Zynq UltraScale+ MPSoC Processing System IP - PS-PL AXI Interfaces do not function correctly at 64-bit or 32-bit widths (or 128-bits for M_AXI_HP0_LPD) 2016.12017.1
(Xilinx Answer 67414)Zynq UltraScale+ MPSoC: 2016.2/2016.1 FSBL unable to load PMU_FW in SD and eMMC boot mode on ZCU102 board 2016.12016.3
(Xilinx Answer 65971)FSBL EL3 stack size is unused 2015.42016.1
(Xilinx Answer 66523)Zynq UltraScale+ MPSoC: FSBL for ZCU102 requires I2C interface2015.4TBD

 

Known issues for XSDK Bootgen

Xilinx AnswerTitleTool Version FoundTool Version Resolved
(Xilinx Answer 68699)SDK 2016.4- Zynq UltraScale+ MPSoC: BootGen doesn't support 64-bit load addresses in .elf files 2016.42017.2
(Xilinx Answer 68396)2016.3/2016.4 SDK - Secure Boot Image fails to boot on Zynq UltraScale+ ES2 Silicon 2106.32017.1
(Xilinx Answer 68170)SDK 2016.3- Zynq UltraScale+ MPSoC: BootGen doesn't support ZU19 parts 2016.32016.4
(Xilinx Answer 66861)Creating a boot image, the destination of the bitstream should be PL instead of A53 2016.12016.2
(Xilinx Answer 65969)Create Boot Image does not support Zynq UltraScale+ MPSoC2015.42016.1
(Xilinx Answer 66383)Zynq UltraScale+ MPSoC - Are Example BIF Files Available for BootGen?2015.4N.A.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64375 Xilinx Zynq UltraScale+ MPSoC Solution Center N/A N/A
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
65971 2015.4 - Zynq UltraScale+ MPSoC: FSBL EL3 stack size is unused N/A N/A
AR# 65467
Date 05/10/2017
Status Active
Type Solution Center
Devices
  • SoC