Version Found: DDR4 v1.0, DDR3 v1.0
AXI enabled DDR3/DDR4 SDRAM IP designs have the data mask incorrectly tied to GND during Read-Modify-Write commands.
The data mask signals should be driven by the AXI layer of the IP based on the write strobes for Read-Modify-Write (RMW) commands.
To fix this issue, the following lines of code inside <ip_name>_ddr3.sv, instance name u_ddr3_mem_intfc:
Go to line 750:
replace it with the following:
Note: Replace "ddr3" with "ddr4" if this is a DDR4 interface.
To prevent Vivado from overwriting the IP edits, it is recommended to create your own IP Repository that contains the RTL edits.
To do this, follow the steps below:
10/12/2015 - Initial Release