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AR# 65730

Vivado - 2014.4 - placement option with large design and failing BRAM paths


In my heavily utilized design, there are several failing timing paths involving BRAMs.

These are normally in the form FIFO -> LUT -> BRAM or BRAM -> BRAM.

After trying several place_design directives, nothing has been successful.

Is there anything else that can be tried?


In this case, to produce better place_design results, you can do the following:

  • Constrain the BRAM locations to be closer together.
  • Use the below parameter which enlarges the area used to place logic in the design.
set_param place.GPTargetDensity 0.7

Here is an image of the placement before these changes.

After the changes, the placement uses more area.

Even if this is successful, it is recommended to start with the default flow and try place_design directives first.

AR# 65730
Date 10/23/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.4.1