When I compile a design for a Virtex device, the "Force GSR" option does not generate a STARTUP_VIRTEX cell in the EDIF netlist.
How can I use the GSR or STARTUP_VIRTEX blocks in my design?
To use the GSR or STARTUP block, STARTUP_VIRTEX must be instantiated. (See the coding example available in the Xilinx Manual "Synthesis and Simulation Design Guide, Chapter 5: Using Dedicated Global Set/Reset Resource," available at:
NOTE: For Virtex designs, Xilinx strongly recommends that users design their own reset networks instead of using GSR, as the secondary routing for reset is much faster than GSR. You may use a STARTUP_VIRTEX cell to reset the entire design, but the recommended method is to use your own reset.
On Virtex devices, the GSR routing can be slower than routing of "manual" reset lines to latches. Therefore, it can be advantageous to not instantiate the STARTUP_VIRTEX block in a Virtex device.
Still, the STARTUP_VIRTEX block can be manually instantiated; if you choose to do this, the default should be to not force GSR. If this is the case, a startup block will not be produced (in order to prevent inadvertent GSR usage).