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AR# 65970

2015.4 SDK - Zynq UltraScale+ MPSoC: usleep() implementation in the BSP assumes a 50MHz clock


usleep() implementation in the BSP assumes a 50MHz clock result in an error on the sleep time.

It also programs the LPD SWDT to divide down the assumed 50MHz clock and counts down the sleep based on reads from the timer value, i.e. it does not treat the timer as read-only. 

This causes issues if multiple BSPs are running concurrently, (for example, on the two R5s), one BSP can be counting down a sleep value while the other one programs it, thereby invalidating the first sleep.


This issue will be fixed in the 2016.1 release of Vivado Design Suite.

AR# 65970
Date 12/03/2015
Status Active
Type General Article
  • Zynq UltraScale+ MPSoC
  • Vivado Design Suite - 2015.4
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