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AR# 66002

Virtex UltraScale FPGA VCU108 Evaluation Kit - Rev 1.0 - JTAG chain might become inactive after configuration


After downloading a bitstream to the VU device on my VC108, I can no longer access the JTAG chain.

Using a different bitstream, the JTAG chain is accessible and works as expected post-configuration.

What could be the reason for this behavior?


The described behavior could be related to FMC pin treatment.

FMC_HPC0_PRSNT_M2C_B connects the FMC U26 Output Enable with the H2 pin on the FMC HPC0 connector J22.

This net is pulled UP with 4.7K to UTIL3V3.

UTIL_3V3 is generated by a dedicated regulator (U156 on page 81 of the board schematics) so this voltage should be always available when the board is powered ON, regardless of the design loaded into the FPGA.

U26 is used to bypass FMC HPC0 when there is no FMC card connected to it (Figure 1-8 UG1066).

FMC_HPC0_PRSNT_M2C_B is also connected to a level converter which then brings the FMC_HPC0_PRSNT_M2C_B_LS net to the UltraScale device pin AL19 on Bank65.

The default state for unused pins in the VU device on the VCU108 is pull-down.

If FMC_HPC0_PRSNT_M2C_B_LS is an unused pin in a particular design, it will be pull-down. FMC_HPC0_PRSNT_M2C_B will be pulled down resulting in the U26 switch being open, and the JTAG chain might not be accessible.66002-3.jpg

If the FMC_HPC0_PRSNT_M2C_B_LS, or the FMC_HPC1_PRSNT_M2C_B_LS pin is not used in a particular design, and the FMC interface is unused, the design needs to set unused pin state to pull-up or pull-none to avoid this problematic behavior.

AR# 66002
Date 11/30/2015
Status Active
Type General Article
  • Virtex UltraScale
Boards & Kits
  • Virtex UltraScale FPGA VCU108 Evaluation Kit