AR# 66173


Design Advisory - Vivado Timing WNS Alert - 7 Series - Missing Timing Arc on BUFR to BUFG clock path causes hold violation


Hold violations are seen between BUFR and BUFG clock domains in the 2015.x releases of Vivado. This is caused by a missing timing arc.



The hold violation is caused by a missing timing arc on the path between BUFR and BUFG.

The work-around is to add clock uncertainty on the BUFG clock domain. 

For example:

create_generated_clock -name genclk -source [get_ports Clk] -divide_by 1 [get_pins Bufg/O]
set_clock_uncertainty -hold 0.290 -from [get_clocks -of [get_pins Bufr/O]] -to [get_clocks -of [get_pins Bufg/O]]

In Vivado 2016.1, the Worst Negative Slack (WNS) will increase by 20-30ps as a result of this issue being fixed. 

We recommend running your routed design through Vivado 2016.1 static timing analysis (report_timing_summary) to determine the impact of this change on your design.

Please remove the 'set_clock_uncertainty' constraint when you migrate to Vivado 2016.1.

AR# 66173
Date 04/18/2016
Status Active
Type Design Advisory
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