This answer record contains the Release Notes and Known Issues for the Zynq UltraScale+ MPSoC Processing System IP and includes the following:
Zynq UltraScale+ MPSoC Processing System IP Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|1.0 (Rev 1)||2015.3|
|1.0 (Rev 2)||2015.4|
The table below provides answer records for general guidance when using the Zynq UltraScale+ MPSoC IP.
|(Xilinx Answer 55248)||Vivado Timing and IP Constraints|
|(Xilinx Answer 65467)||Zynq UltraScale+ MPSoC - Boot and Configuration|
|(Xilinx Answer 64375)||Xilinx UltraScale+ MPSoC Solution Center|
|Zynq UltraScale+ MPSoC - Silicon Revision Differences|
|(Xilinx Answer 66071)||Design Advisory for Zynq UltraScale+ MPSoC Devices|
Known and Resolved Issues
The following table provides known issues for the Zynq UltraScale+ MPSoC, starting with v1.0 (Rev 2), released in the Vivado 2015.4 tool.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version |
|(Xilinx Answer 67861)||Design Advisory for Zynq UltraScale+ MPSoC Processing System - How do I upgrade from Vivado 2016.2 and earlier?||2016.3||N/A|
|(Xilinx Answer 68184)||PS LPDDR4 devices do not complete psu_init initialization||2016.3||2016.4|
|(Xilinx Answer 65982)||Zynq UltraScale+ MPSoC, Vivado 2015.4 - Patch for PS DDR3/DDR4/LPDDR4 and GTR transceiver support||2015.4||2016.1|
|(Xilinx Answer 66218)||Zynq UltraScale+ MPSoC - psu_init flow is not working due to difference between psu_int.c and psu_init.tcl||2015.4||2016.1|
|(Xilinx Answer 66219)||Zynq UltraScale+ MPSoC - Bringing Processors out of reset by configuring the Processor Block level software controlled reset registers in JTAG mode||2015.4||2016.1|
|(Xilinx Answer 66295)||Zynq UltraScale+ MPSoC - PS-PL AXI Interfaces do not function correctly at 64- or 32-bit widths (or 128-bits for M_AXI_HP0_LPD)||2015.4||2016.3|
|(Xilinx Answer 66220)||Zynq UltraScale+ MPSoC - Reset Signal Availability for PS+PL designs||2015.4||2016.1|
|(Xilinx Answer 66223)||Zynq UltraScale+ MPSoC - DRC with default configuration for DDR||2015.4||2016.1|
|(Xilinx Answer 66224)||Zynq UltraScale+ MPSoC - Zynq UltraScale+ MPSoC wrapper throws syntax error when project is set to VHDL - for PS-only design||2015.4||2016.1|
|(Xilinx Answer 66225)||Zynq UltraScale+ MPSoC - Limitations with hand-off to software (SDK) when we have segments created in memory to be accessible from a specific master||2015.4||2016.1|
|(Xilinx Answer 66226)||Zynq UltraScale+ MPSoC - Failure while creating an application for MicroBlaze with PS DDR as code execution memory||2015.4||2016.1|
|(Xilinx Answer 66227)||Zynq UltraScale+ MPSoC - Use of Split clock with slave interface||2015.4||2016.1|
|(Xilinx Answer 66247)||Zynq UltraScale+ MPSoC - Slightly different PS power numbers reported between Windows and Linux hosts||2015.4||2016.1|
|(Xilinx Answer 66045)||Zynq UltraScale+ MPSoC - How do I connect the UART MODEM signal to EMIO while using MIO?||2015.4||2016.1|
|(Xilinx Answer 66571)||Zynq UltraScale+ MPSoC - Processor System IP GUI Limitations with PS DDR topologies||2015.4||2016.1|
12/12/2015 - Initial release