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AR# 66319

Vivado Synthesis - Using procedures with inouts inside a clocked process statement causes logic to be left out


When using procedures inside clocked process statements, if one of the ports of the procedure is an inout, the logic can get lost.

For example :

procedure my_proceed (signal x : inout;  signal y : in std_logic) is...



Then later in the RTL:

process(clk)  begin


The synthesis tool will get confused by this and can drop the logic associated with the "a" signal.


Currently, it is not recommended that you use procedures at all inside clocked process statements. 

Flop inference can be affected by this and it is recommended to just state the logic outside of the process statement.

AR# 66319
Date 10/28/2016
Status Active
Type Known Issues
  • Vivado Design Suite
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