UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66319

Vivado Synthesis - Using procedures with inouts inside a clocked process statement causes logic to be left out

Description

When using procedures inside clocked process statements, if one of the ports of the procedure is an inout, the logic can get lost.

For example :

procedure my_proceed (signal x : inout;  signal y : in std_logic) is...

...

...

Then later in the RTL:

process(clk)  begin

my_proceed(a,b);

The synthesis tool will get confused by this and can drop the logic associated with the "a" signal.

Solution

Currently, it is not recommended that you use procedures at all inside clocked process statements. 

Flop inference can be affected by this and it is recommended to just state the logic outside of the process statement.

AR# 66319
Date Created 12/29/2015
Last Updated 10/28/2016
Status Active
Type Known Issues
Tools
  • Vivado Design Suite