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AR# 66951

UltraScale/UltraScale+ Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check


Version Found: DDR4 v2.0, DDR3 v1.2, RLDRAM v1.2, QDRII+ v1.2, QDRIV v1.1

Version Resolved: See (Xilinx Answer 58435)

When running report_drc the following warning message might be seen:

WARNING: [DRC 23-20] Rule violation (PDCN-1569)
PDCN #1 Warning Used physical LUT pin 'A3' of cell u_ddr4_0_default/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/microblaze_I/MicroBlaze_Core_I/Area.Core/Byte_Doublet_Handle_I/Use_Dynamic_Bus_Sizing.Not_Using_Reverse_Mem_Instr.EXT_DATA_WRITE_MUX_MSB_I/GEN4_LOOP[0].BYTESTEER_LUT6/Using_FPGA.Native/LUT5 (in u_ddr4_0_default/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/microblaze_I/MicroBlaze_Core_I/Area.Core/Byte_Doublet_Handle_I/Use_Dynamic_Bus_Sizing.Not_Using_Reverse_Mem_Instr.EXT_DATA_WRITE_MUX_MSB_I/GEN4_LOOP[0].BYTESTEER_LUT6/Using_FPGA.Native macro) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A5))+((~A1)*A2*A5)'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.


These warning messages are coming from MicroBlaze and are safe to ignore.

Revision History:

04/16/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 66951
Date 01/12/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite - 2016.1
  • MIG UltraScale
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