We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66954

2016.1 and newer Vivado Hardware Manager - Intermittent configuration failures can occur when the FPGA is power cycled and the programming cable is connected.


The following behavior is new to the Vivado 2016.1 Hardware Manager: When a board is powered off or a cable is disconnected, Vivado will close the hardware target in Hardware Manager.

When the board is powered back on or the cable is reconnected, Vivado will now automatically attempt to re-open the hardware target in Hardware Manager.

In addition to reopening the hardware target, Hardware Manager will attempt to refresh all device registers including reading configuration status registers.

Due to this new behavior it is possible to see intermittent configuration failure occur if all of the following are true:

  • Any configuration interface other than JTAG is used
  • Vivado Hardware Manager is open with a Digilent or Xilinx USB programming cable connected
  • Board is power cycled or powered on

If any configuration interface (except JTAG) is used and the JTAG cable is also connected, it is possible that the configuration will be interrupted by the JTAG chain auto detection and/or register reads and will not complete configuration at power up or power cycle.

Please Refer to (UG908) for additional details.


The issue could occur under three conditions:

  1. Device power on or power cycle. Pulsing PROGRAM_B does not result in this issue because the Vivado Hardware Manager does not see a cable disconnection and perform the cable auto detection.
  2. User issues "refresh_hw_devices" command
  3. User plugs in the JTAG cable

Potential Work-arounds include the following:

1) Set the following parameter to disable the power up detection

set_param labtools.auto_update_hardware 0

Note: The above parameter can be set in the init.tcl file in Vivado.

Additional information on init.tcl:

When you start the Xilinx Design tools, it looks for the init.tcl initialization script in two different locations:

1) In the software installation: installdir/Vivado/version/scripts/init.tcl

installdir is the installation directory where the Vivado Design Suite is installed.

2) In the local user directory:

  1. For Windows 7: %APPDATA%/Roaming/Xilinx/Vivado/init.tcl
  2. For Linux: $HOME/.Xilinx/Vivado/init.tcl

If init.tcl exists in both of these locations, Vivado sources the file from the installation directory first, and then from your home directory.

For more information, see the Loading and Running Tcl Scripts chapter in (UG894) Vivado Design Suite User Guide Using Tcl Scripting.


2) Unplug the cable prior to power up or power cycle.

3) Slow down occurrence of the polling.

For example to poll once an hour, launch hw_server with the following option:

hw_server -e "set jtag-poll-delay 3600000000"

4) Close and reopen the target in JTAG mode as follows to prevent any polling from happening, then restore back to normal mode:

a) Close and reopen the target in JTAG mode:

set tmp_target [ get_hw_targets -filter { IS_OPENED == 1 }]
close_hw_target $tmp_target
open_hw_target -jtag_mode on $tmp_target
set_property LOCK true [get_property  HW_JTAG $tmp_target]

b) Restore back to normal mode once the part has booted:

set_property LOCK false [get_property  HW_JTAG $tmp_target
close_hw_target $tmp_target
open_hw_target $tmp_target
AR# 66954
Date 03/13/2017
Status Active
Type General Article
  • Vivado Design Suite