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AR# 67106

High Speed SelectIO Wizard - Simulation fails when using IES simulator

Description

Version Found: 2016.1

Simulation of the High Speed SelectIO core fails when using the IES simulator due to issues with the bit-widths for the parameters set by the Wizard. 

Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)

Solution

To work around this issue, you will need to increase the bit-widths for all parameters:

For example, Vivado generates the parameters as shown:

    .C_DIFF_EN('B0000011111111000000000000000000000000000000000000000),
        .C_RX_PIN_EN('B0000001010101000000000000000000000000000000000000000),
        .C_RX_BITSLICE_EN('B0000011111111000000000000000000000000000000000000000),
        .C_ALL_RX_EN('B0000011111111000000000000000000000000000000000000000),
   

This should be changed to the following:

        .C_DIFF_EN(52'B0000011111111000000000000000000000000000000000000000),
       .C_RX_PIN_EN(52'B0000001010101000000000000000000000000000000000000000),
       .C_RX_BITSLICE_EN(52'B0000011111111000000000000000000000000000000000000000),
        .C_ALL_RX_EN(52'B0000011111111000000000000000000000000000000000000000),

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 67106
Date Created 04/26/2016
Last Updated 06/24/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale