Version Found: 2016.1
Simulation of the High Speed SelectIO core fails when using the IES simulator due to issues with the bit-widths for the parameters set by the Wizard.
Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
To work around this issue, you will need to increase the bit-widths for all parameters:
For example, Vivado generates the parameters as shown:
This should be changed to the following: