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AR# 67172

Virtex-7 FPGA Gen3 Integrated Block for PCI Express/AXI Bridge for PCI Express Gen3 (Vivado 2016.1) - Example Design Simulation with VCS Simulator hangs indefinitely

Description

Version Found

  • v2.1 (AXI Bridge for PCI Express Gen3)
  • v4.2 (Virtex-7 FPGA Gen3 Integrated Block for PCI Express)

Version Resolved and other Known Issues

See (Xilinx Answer 61898) for AXI Bridge for PCI Express Gen3
See (Xilinx Answer 54645) for Virtex-7 FPGA Gen3 Integrated Block for PCI Express

When simulating Virtex-7 FPGA Gen3 Integrated Block for PCI Express or AXI Bridge for PCI Express Gen3 (for both Virtex-7 and UltraScale) example designs with VCS simulator in Vivado 2016.1, simulation hangs indefinitely.

Solution

This is a known issue to be fixed in a future release of the core. To work around the issue, please follow the steps below.


  1. Create the Vivado project
  2. Select the VC709 board [applicable for 7 Series Gen3 capable device]
  3. Select PCIe Gen3 Core, Virtex-7 FPGA Gen3 integrated Block for PCIe (or AXI Bridge for PCI Express Gen3).
  4. Open the example design.
  5. In simulation settings, change the target simulator to VCS simulator.
  6. Run The following in the Tcl console.
    launch_simulation -scripts_only
  7. Go to the directory <project/ pcie3_7x_0_example/pcie3_7x_0_example.sim/sim_1/behav>.
  8. Open elaborate.sh and change the VCS command line as follows:
    vcs_opts="-full64 +rad -debug_access+all -debug_region=cell+lib -t ps -licqueue -l elaborate.log".
  9. Run compile.sh by using the following command:
    ./compile.sh
  10. Run elaboration.sh by using the following command:
    ./elaborate.sh
  11. Change simulation run time to 1000ns from 1000000ns in the board_simulate.do file present under the behav directory.
  12. Run simulation.sh by using the following command:
    ./simulation.sh

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

05/12/2016 - Initial Release

AR# 67172
Date Created 05/06/2016
Last Updated 05/20/2016
Status Active
Type Known Issues
IP
  • AXI PCIe Gen3
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)