Version Resolved and other Known Issues:
When simulating Virtex-7 FPGA Gen3 Integrated Block for PCI Express or AXI Bridge for PCI Express Gen3 (for both Virtex-7 and UltraScale) example designs with VCS simulator in Vivado 2016.1, simulation hangs indefinitely.
This is a known issue to be fixed in a future release of the core. To work around the issue, please follow the steps below.
Note: "Version Found" refers to the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
05/12/2016 - Initial Release