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AR# 67224

UltraScale/UltraScale+ Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCM


Version Found: DDR4 v2.0, DDR3 v1.2, RLDRAM v1.2, QDRII+ v1.2, QDRIV v1.0

Version Resolved: See (Xilinx Answer 58435)

(PG150) states to use the following XDC syntax for the CLOCK_DEDICATED_ROUTE constraint:

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets net_name]

However, when this syntax is used the following error message occurs:

ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ddr3_refclk_i] >


The CLOCK_DEDICATED_ROUTE BACKBONE constraint does not work properly with Vivado unless it is applied to the input pin of the MMCM the BUFGCE is driving.

Therefore, the following syntax example should be used:

[get_pins -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1}]

The CLOCK_DEDICATED_ROUTE BACKBONE syntax will be updated in a future release of (PG150).

Revision History:

05/13/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 67224
Date 01/17/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite - 2016.1
  • MIG UltraScale
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