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AR# 67437

2016.2 [PLIDC-14] DRC warning seen during Implementation for 7 Series designs


I see the following DRC warning during Implementation of a 7 Series design:

[DRC 23-20] Rule violation (PLIDC-14) IDELAYCTRL REFCLK should be same as ISERDES CLK - The BITSLICE cell IDELAYCTRL system_i/Interface_0/inst/U_idelayctrl REFCLK pin should be driven by the same clock net as the associated ISERDES system_i/Interface_0/inst/U_adc_if/genblk1[0].ISERDESE2_inst CLK or CLKDIV pin.

Can this be ignored?


The tool is incorrectly issuing this message for 7 Series designs. This message can be safely ignored if you are using a 7 Series or Zynq device. This issue has been fixed in the 2016.3 release.

AR# 67437
Date 11/24/2016
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2016.2
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