We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67977

Vivado 2016.1/2 - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check


I received the following DRC warning during bitstream generation:

WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check - Used physical LUT pin 'A1' of cell LUT6_2_inst/LUT5 (in LUT6_2_inst macro) is not included in the LUT equation: 'O5=(A2*A5)'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.

The message is repeated for LUT pin 'A3' and 'A4'.

What does this DRC message mean and does this issue affect functionality?


The DRC check is intended to verify that the LUT configuration is consistent with its connectivity. In this example the DRC message is invalid.

The LUT6_2 is a macro containing both a LUT5 and a LUT6. While it is true that the equation of the O5 LUT does not use all input pins, the O6 LUT uses all of the input pins and so the configuration is valid. 

This issue has been fixed in Vivado 2016.3, and this incorrect DRC warning no longer occurs.

AR# 67977
Date 11/01/2016
Status Active
Type General Article
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
Page Bookmarked