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AR# 68065

2016.3: SDK - While debugging on Zynq/Zynq MPSoC, triggering a processor core reset from outside of the debugger causes the core to halt at the reset vector

Description

In the 2016.3 release of SDK, While debugging on Zynq/Zynq MPSoC, triggering a processor core reset from outside of the debugger causes the core to halt at the reset vector.

How can I resolve this?

Solution

The Debugger enables the vector catch to halt the processor core at the reset vector when a core reset is triggered.

If it is not desirable to halt the core at the reset vector, you can disable debugger access to that core, so that the vector catch is not turned on and the core does not stop at the reset vector. Access can be disabled from XSDB, as follows:

  1. Select the processor core from the XSDB targets list
  2. Run the following command:
configparams disable-access 1

For Example:

xsct% ta

  1  APU

  2  ARM Cortex-A9 MPCore #0 (Breakpoint)

  3 * ARM Cortex-A9 MPCore #1 (Breakpoint)

  4  xc7z020

xsct% configparams disable-access 1
AR# 68065
Date Created 10/12/2016
Last Updated 10/14/2016
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2016.3