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AR# 68069

UltraScale+ PCI Express Integrated Block (Vivado 2016.3) - CPLL Calibration Block Integration and MSI-X Core GUI Issue

Description

Version Found: v1.1 Rev2 (Vivado 2016.3)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

This answer record provides a tactical patch to fix the following two issues with the UltraScale+ PCI Express Integrated Block core in Vivado 2016.3.

  1. Integration of CPLL Calibration Block
  2. Core GUI Issues:
    • PF1 MSI-X is not customizable
    • cfg_interrupt_sent port that is shared by MSI and MSI-X is not exposed when MSI-X is enabled



This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

The issues listed above will be fixed in a future release of the core, please install the tactical patch attached as described below:

METHOD 1:

  1. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist)
  2. Extract the contents of the ".zip" archive to a directory starting with the name AR68069.
    Note: most extraction tools will allow you to automatically create a directory with the same name as the zip file
  3. Run Vivado software tools from the original install location.


METHOD 2:

  1. Create a separate directory for the patched files
  2. Extract the contents of the ".zip" archive to the desired patch directory location
  3. Set the MYVIVADO environment variable to point to the Vivado directory under this patch directory
    For example:
    set MYVIVADO=C:\MYVIVADO\vivado-patch-AR68069\vivado\
  4. Run Vivado software tools from the original install location.

Note: The "Version Found" column lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

11/21/2016 - Updated patch rev1 to rev4:
10/14/2016 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR68069_Vivado_2016_3_preliminary_rev4.zip 1 MB ZIP
AR# 68069
Date Created 10/21/2015
Last Updated 11/22/2015
Status Active
Type Known Issues
IP
  • UltraScale+ FPGA Integrated Endpoint Block for PCI Express