Version Found: V1.3 (Rev. 1)
Version Resolved: See (Xilinx Answer 69038)
GSI QDRII+ memory models produce actual data errors during simulation.
The simulation can also fail as a result of the memory model not returning a data edge aligned with the CQ/CQ# clock to emulate noise.
Because MIG UltraScale does not support full calibration during behavioral simulations, the misaligned data and clock will not be aligned properly and might still cause data failures.
GSI components are not native to Vivado.
A custom CSV will need to be implemented in order to use the component. Xilinx does not officially support Custom CSVs during simulation.
To work around the issue, you will need to adjust some parameters in the model.
This can be done by changing the "tCQHQV" and "tCQHQX" parameters in the Verilog memory model.
tCQHQV <= 0.00 ns
tCQHQX <= 0.00 ns
For more information, contact GSI directly.
04/19/2017 - Initial Release