Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.
This Design Advisory covers the Kintex UltraScale+ and Virtex UltraScale+ families.
Design Advisory Alerted on August 13th, 2018
|(Xilinx Answer 71371)||Design Advisory for UltraScale+ GTH GTY I, M and Q grade - Data errors are occasionally seen on extreme temperature ramps|
Design Advisory Alerted on June 19th, 2017
|(Xilinx Answer 69152)||Design Advisory 2017.1 Tactical Patch for Vivado bi-directional logic issue using component mode primitives (IOBUF usage with IDDRE1, ISERDESE3, ODDRE1, OSERDESE3, or FDCE/FDPE/FDRE/FDSE with IOB=TRUE)|
|(Xilinx Answer 69034)|
Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential I/O Standards
|(Xilinx Answer 68832)||Design Advisory for UltraScale FPGA, UltraScale+ FPGA, and Zynq UltraScale+ MPSoC eFUSE Programming with Vivado 2016.4 (and earlier)||[SECURITY]|
|(Xilinx Answer 67645)||Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation||[SECURITY]|