AR# 69525


MIPI CSI-2 TX Subsystem - How is the Frame End generated?


The Frame Start can be asserted using tuser[0] on the AXI4-Stream interface, but there is no interface to trigger Frame End. 

How is the Frame End generated in the MIPI CSI-2 TX Subsystem?


The MIPI CSI-2 TX Interface has no definition for Frame End at the AXI-4 stream interface, and the IP handles the generation of the Frame End.

Vivado 2018.1 and later:

In Vivado 2018.1, the MIPI CSI-2 TX Subsystem v4.1 has a new option to enable a register which allows the user to generate a Frame End based on the number of lines. 

This must be selected at the time of generation in the configuration GUI.

Vivado 2017.4 and earlier:

The Frame End short packet will be automatically generated and sent from MIPI CSI-2 TX Subsystem whenever the user asserts the Frame start (tuser[0]) to send the next frame.

Another way of looking at this is that the Frame End packet will be sent after the user starts sending a new frame.

When using the MIPI CSI-2 TX Subsystem, the Frame End will always be close to the Frame Start. 

All the image/non-image data should be transmitted normally, but the user might see that in some cases there will be a big gap between last data packet and Frame end packet.

This is expected behavior of the MIPI CSI-2 TX Subsystem and is still compliant with the MIPI CSI-2 specification, because there is no clear description in the specification that prohibits this behavior. 

There is a recommendation (informative and not a requirement) in the MIPI specification to make sure that the spacing between the last data packet and Frame End packet should be as close as possible to the minimum packet spacing. 

The intention is to ensure that the Frame Start and Frame End packets accurately denote the start and end of a frame of image data.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
65242 MIPI CSI-2 Receiver Subsystem - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
69530 LogiCORE MIPI D-PHY and MIPI CSI-2 RX Subsystem - How much margin is in the MIPI D-PHY RX line rate settings? N/A N/A
AR# 69525
Date 04/09/2018
Status Active
Type General Article
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