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AR# 70027

2017.3 Vivado - Clocking Wizard IP core is not displayed in the Vivado hierarchy

Description

I have a design that instantiates a Clocking Wizard IP core with the instance name of XPLL.

In Vivado 2017.2, this IP core was shown correctly in the hierarchy source view (HSV).

However, in Vivado 2017.3, HSV shows as missing source for the XPLL.

Running synthesis will fail due to the missing source.

Solution

This issue will affect any IP core that is given the same name as a Xilinx FPGA primitive.

XPLL is the name of an FPGA primitive.

The Vivado HSV should have a check to distinguish the IP core instantiation from a primitive instantiation and send the correct files to synthesis. 

HSV correctly makes the distinction for standard HDL modules but fails if the instance is an IP core.

Until this is fixed, users should change the instance name in their design.

AR# 70027
Date 10/25/2017
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2017.3
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