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AR# 70027

2017.3 Vivado - Clocking Wizard IP core is not displayed in the Vivado hierarchy


I have a design that instantiates a Clocking Wizard IP core with the instance name of XPLL.

In Vivado 2017.2, this IP core was shown correctly in the hierarchy source view (HSV).

However, in Vivado 2017.3, HSV shows as a missing source for the XPLL.

Running synthesis will fail due to the missing source.


This issue will affect any IP core that is given the same name as a Xilinx FPGA primitive.

XPLL is the name of an FPGA primitive.

The Vivado HSV should have a check to distinguish the IP core instantiation from a primitive instantiation and send the correct files to synthesis. 

HSV correctly makes the distinction for standard HDL modules but fails if the instance is an IP core.

This issue is fixed in Vivado 2017.4.  To avoid the issue in Vivado 2017.3 and earlier, users must change the instance name in their design.

AR# 70027
Date 12/21/2017
Status Active
Type General Article
  • Vivado Design Suite - 2017.3
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