AR# 70060

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** Fatal: (vsim-3693) The minimum time resolution limit (1fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units

Description

I have encountered the following error when simulating a design that contains GTHE4 or GTYE4 transceivers, such as the IEEE RS-FEC cores example designs.

This only occurs when the simulator language is set to VHDL.

** Fatal: (vsim-3693) The minimum time resolution limit (1fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.

Where does the resolution 1fs come from? How can I resolve the error?

Solution

UltraScale+ GTHE4 or GTYE4 transceiver models have a 1fs resolution set.

The reason for the introduction of the 1fs resolution is to support the "PCIe Gen4 separate reference clock independent SSC clocking scheme".

Support for spread spectrum clocking means that higher precision is required.

The same issue is also present for GTM_DUAL and RFDAC/RFADC SECUREIP.


To fix the error, you can try any of the following methods:

  • Change the timescale in the top level test bench file: `timescale 1ps/1fs.
  • Run vsim with the "-t 1fs" command line option.
  • Change your target simulation language from VHDL to Verilog or Mixed.
AR# 70060
Date 02/13/2020
Status Active
Type General Article
Tools
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