AR# 71554

|

Queue DMA subsystem for PCI Express (PCIe) (Vivado 2018.2) - [Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I1

Description

When the "AXI-lite slave interface" option is enabled, the following error is observed during the opt_design phase when going through the Vivado implementation process with an IP example design.


[Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic.
The LUT cell name is: qdma_0_i/inst/udma_wrapper/dma_top/base/CFG_INST/s_axil_wready_INST_0.



This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

To fix the issue, drive the S_AXI_LITE interface ports as shown below in the xilinx_dma_pcie_ep.sv file (File path: /qdma_0_ex/imports/xilinx_dma_pcie_ep.sv)

      // AXI-Lite Interface
      .s_axil_awaddr   (32'b0),
      .s_axil_awuser   (8'b0),
      .s_axil_aruser   (8'b0),
      .s_axil_awprot   (3'b0),
      .s_axil_awvalid  (1'b0),
      .s_axil_awready  (),
      .s_axil_wdata    (32'b0),
      .s_axil_wstrb    (4'b0),
      .s_axil_wvalid   (1'b0),
      .s_axil_wready   (),
      .s_axil_bvalid   (),
      .s_axil_bresp    (),
      .s_axil_bready   (1'b0),
      .s_axil_araddr   (32'b0),
      .s_axil_arprot   (3'b0),
      .s_axil_arvalid  (1'b0),
      .s_axil_arready  (),
      .s_axil_rdata    (),
      .s_axil_rresp    (),
      .s_axil_rvalid   (),
      .s_axil_rready   (1'b0),
 

This issue will be fixed in the next release of the core.

Revision History:

11/15/2018 - Initial Release

AR# 71554
Date 11/15/2018
Status Active
Type General Article
Devices
Tools
IP
People Also Viewed