UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 71697

UltraScale+ RFSoC DDR4/DDR3/RLDRAM3 - The FSVE1156 package allows incorrect data widths

Description

Version Found: DDR4 v2.2 (Rev. 5), DDR3 v1.4 (Rev. 5), RLDRAM3 v1.4 (Rev. 5)

Version Resolved: For DDR4 (Xilinx Answer 69035), For DDR3 (Xilinx Answer 69036), For RLDRAM3 (Xilinx Answer 69037)

If I target an FSVE1156 RFSoC package in Vivado 2018.2 and earlier releases, the tool allows a 64-bit SODIMM topology.

However, when the Output Products are generated, an error is produced.

Solution

In Vivado 2018.3, the FSVE1156 RFSoC package now limits All Memory IP to only have component topologies, as per package restrictions.

Revision History:

05/08/2019 - Initial Release

Linked Answer Records

Master Answer Records

AR# 71697
Date 05/09/2019
Status Active
Type General Article
Devices
Tools
IP More Less
Page Bookmarked