Version Found: DDR4 v2.2 (Rev. 5), DDR3 v1.4 (Rev. 5), RLDRAM3 v1.4 (Rev. 5)
If I target an FSVE1156 RFSoC package in Vivado 2018.2 and earlier releases, the tool allows a 64-bit SODIMM topology.
However, when the Output Products are generated, an error is produced.
In Vivado 2018.3, the FSVE1156 RFSoC package now limits All Memory IP to only have component topologies, as per package restrictions.
05/08/2019 - Initial Release