AR# 71961
Design Advisory for Zynq UltraScale+ MPSoC ZCU102 and ZCU106 Evaluation Kits - DDR4 SODIMM change
Description
Due to an End of Life notification from Micron Technology, Inc. the DDR4 SODIMM part on the ZCU102 Evaluation Kit and the ZCU106 Evaluation Kit has changed.
PCN_32423 has been issued by Micron, which includes the MTA8ATF51264HZ-2G6B1 (x8b DDR4) part which is on the ZCU102 and ZCU106 boards.
Solution
PCN_32423 from Micron states that the recommended replacement for the MTA8ATF51264HZ-2G6B1 is the MTA4ATF51264HZ-2G6E1 x16b DDR4 part.
Both the ZCU102 and ZCU106 boards have been updated and now ship with this recommended replacement DDR4 SODIMM installed.
Boards Affected:
- ZCU102 Evaluation Kits labeled 0432055-01 through 0432055-04 are shipped with SODIMM MTA8ATF51264HZ-2G6B1.
- ZCU102 Evaluation Kits labeled 0432055-05 onward are shipping with SODIMM MTA4ATF51264HZ-2G6E1.
- ZCU106 Evaluation Kits labeled 0432032-01 are shipped with SODIMM MTA8ATF51264HZ-2G6B1.
- ZCU106 Evaluation Kits labeled 0432032-02 onward are shipping with SODIMM MTA4ATF51264HZ-2G6E1.
Impact:
The change in the component width means that different memory settings are required during the FSBL for designs to function.
A decrease in performance is possible due to there being one less bank bit in x16 component topologies.
Resolution:
Starting in Vivado 2018.3, when targeting a ZCU102/ZCU106 board, the FSBL will have a custom function to query the SPD prom on the DIMM to determine which DIMM is being used.
It will then use the correct DDR settings, using a single image. This means that any applications that use the newer DIMMs will need to be rebuilt with a new FSBL generated from SDK 2018.3 or later.
Vivado 2018.3 users should also apply the patches in (Xilinx Answer 72113).
Note: The psu_init.tcl can no longer be used on ZCU102 boards as it does not contain the dynamic SPD setting algorithm.
ZCU102 designs should now uncheck the Run psu_init checkbox in the Debug/Run Configurations of SDK, and instead first run an FSBL application before downloading and debugging a target executable.
See (Xilinx Answer 72210) for more details.
SDK will not be updated to create and download a FSBL project before debugging.
Work-around:
- To offset any performance loss, consider setting the PSU__DDRC__DDR4_ADDR_MAPPING parameter on the Zynq UltraScale+ MPSoC Processing System block to 1 for a more-optimized bank utilization.
- For Vivado versions prior to 2018.3, it is also possible to change the Zynq UltraScale+ MPSoC Processing System IP settings to target specific DIMM settings statically. Use the following settings:
| Parameter | Old DIMM | New DIMM |
| DRAM IC Bus Width (per die) | 8 | 16 |
| DRAM Device Capacity (per die) | 4096 | 8192 |
| Bank Group Address Count | 2 | 1 |
| Row Address Count | 15 | 16 |
Note: for any design updated from an older version of the Vivado Board Files (2018.2), the user might need to manually update their Vivado Project Settings to point to the latest board revision.
Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 66752 | Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| 68819 | Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 72113 | Zynq UltraScale+ MPSoC, PS DDR - DDR4 training occasionally fails on ZCU102 and ZCU106 boards using newer DIMMs | N/A | N/A |
| 71747 | Zynq UltraScale+ MPSoC/RFSoC, PS DDR - FSBL must be used to initialize PS DDR designs with ECC | N/A | N/A |
| AR# 71961 | |
|---|---|
| Date | 07/11/2019 |
| Status | Active |
| Type | Design Advisory |
| Devices | |
| IP | |
| Boards & Kits | |