This answer record contains the Release Notes and Known Issues for the Versal ACAP PHY for PCI Express Core and includes the following:
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
Supported devices can be found in the following locations:
The following table provides a list of tactical patches for the Versal ACAP PHY for PCI Express core applicable on corresponding Vivado tool versions.
|Answer Record||Core Version (After installing the Patch)||Tool Version|
|(Xilinx Answer 75572)||v1.0 (Rev 75572)||2020.1|
Known and Resolved Issues
The following table provides known issues for the Versal ACAP PHY for PCIExpress core.
Note: The "Version Found" column lists the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 75572)||Versal ACAP PHY for PCI Express (Vivado 2020.1) - phy_rxdata is stuck at zero in Gen4 configuration||Vivado 2020.1||Vivado 2020.2|
Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
|05/13/2020||Added (Xilinx Answer 75572)|