AR# 72289

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Versal ACAP PHY for PCI Express - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the Versal ACAP PHY for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

Supported devices can be found in the following locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Tactical Patch

The following table provides a list of tactical patches for the Versal ACAP PHY for PCI Express core applicable on corresponding Vivado tool versions.

Answer RecordCore Version (After installing the Patch)Tool Version
(Xilinx Answer 75572)v1.0 (Rev 75572)2020.1

Known and Resolved Issues

The following table provides known issues for the Versal ACAP PHY for PCIExpress core.

Note: The "Version Found" column lists the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 75572)Versal ACAP PHY for PCI Express (Vivado 2020.1) - phy_rxdata is stuck at zero in Gen4 configurationVivado 2020.1Vivado 2020.2

Other Information:

  • NA

Xilinx Forums:

Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support.

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

 

Revision History:

09/09/2019Initial Release
05/13/2020Added (Xilinx Answer 75572)

 

AR# 72289
Date 05/13/2021
Status Active
Type Release Notes
IP
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