AR# 72747

DMA Subsystem for PCI Express in "AXI-Bridge" mode (Vivado 2019.1) - "NUM_READ_OUTSTANDING" and "NUM_WRITE_OUTSTANDING" parameters of M_AXI_B port reset to "2" after validate BD is executed in IP Integrator

Description

Version Found: v4.1 (Rev3)

Version Resolved and other Known Issues: (Xilinx Answer 65443)

the "NUM_READ_OUTSTANDING" and "NUM_WRITE_OUTSTANDING" parameters of the M_AXI_B port are reset to "2" after "Validate BD Design" is executed in IP Integrator. 

No matter what the value is set to in the GUI, it is always reset to 2. 

The tactical patch provided in this answer record contains a fix for this issue.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

For instruction on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

11/08/2019 - Initial Release


Attachments

Associated Attachments

Name File Size File Type
AR72747_Vivado_2019_1_preliminary_rev1.zip 5 MB ZIP
AR# 72747
Date 11/08/2019
Status Active
Type Known Issues
Devices
Tools
IP