AR# 73714


UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardware


Version Found:
  • DDR4 v2.2 (Rev. 9)
  • DDR3 v1.4 (Rev. 9)
  • RLDRAM3 v1.4 (Rev. 9)
  • QDRII+ v1.4 (Rev. 9)
  • QDRIV v2.0 (Rev. 9)
  • LPDDR3 v1.0 (Rev. 9)

Version Resolved: See (Xilinx Answer 58435)

Due to a change with the DONT_TOUCH attribute in Vivado 2020.1, locked IPs generated in earlier versions of Vivado will encounter errors during implementation or while running in hardware when used in Vivado 2020.1 and later.

The issue will manifest as implementation errors or calibration failures depending on the IP and configuration.


To prevent errors during implementation or while running in hardware, the following parameter must be added to the design before running synthesis:

set_param project.replaceDontTouchWithKeepHierarchySoft 1

This behavior only applies to designs generated prior to 2020.1, and then brought in to 2020.1 or later, while also keeping the IP locked without upgrading to the current version of Vivado.

If the IP is generated in Vivado 2020.1 or later, or if the IP was from an earlier version and then brought in to 2020.1 or later and upgraded, then this parameter does not need to be set and no additional actions are required.

For DDR3/DDR4 designs using RDIMMs with Self-Refresh see (Xilinx Answer 73715)

Revision History:

06/03/2020 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A

Child Answer Records

AR# 73714
Date 06/04/2020
Status Active
Type Known Issues
Devices More Less
IP More Less
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