AR# 75572

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Versal ACAP PHY for PCI Express (Vivado 2020.1) - phy_rxdata is stuck at zero in Gen4 configuration

Description

Version Found:

  • Versal ACAP PHY for PCI Express v1.0 (Rev2) [Vivado 2020.1]

Version Resolved and other Known Issues: (Xilinx Answer 72289)

The patch provided with this answer record fixes an issue where in Gen4 configuration, phy_rxdata is stuck at zero. The pattern generator does not support 32-bit @ 500MHz.

  • The issues are observed in both simulation and hardware.
  • PCIe Gen1/2/3 operations are not affected.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

This a known issue to be fixed in a future version of the core.

A patch for the Versal ACAP PHY for PCI Express core in for Vivado 2020.1 is included in the ZIP file attached to this answer record.

The attached ZIP file contain a "readme" file which include installation instructions.

Revision History:

  • 05/13/2020 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR75572_Vivado_2020_1_preliminary_rev1.zip 119 KB ZIP
AR# 75572
Date 05/13/2021
Status Active
Type Known Issues
Devices
IP
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