Version Resolved and other Known Issues: (Xilinx Answer 72289)
The patch provided with this answer record fixes an issue where in Gen4 configuration, phy_rxdata is stuck at zero. The pattern generator does not support 32-bit @ 500MHz.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
This a known issue to be fixed in a future version of the core.
A patch for the Versal ACAP PHY for PCI Express core in for Vivado 2020.1 is included in the ZIP file attached to this answer record.
The attached ZIP file contain a "readme" file which include installation instructions.
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