AR# 7598


CPLD - What is the difference between CPLDs and FPGAs?


What is the difference between a CPLD and an FPGA?


CPLDs, with their PAL-derived, easy-to-understand AND-OR structure, offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. 

Once programmed, the design can be locked and thus made secure. Most CPLD architectures are very similar, so it is important to evaluate the subtle nuances. In-system-programmability is a must for today's designs, and the ability to maintain pin-outs during design modifications ("pin-locking") is crucial. 

The limited complexity (<500 flip-flops) means that most CPLDs are used for "glue logic" functions. In older families, the high static (idle) power consumption prohibits their use in battery-operated equipment.

Cool Runner devices are the notable exception, as they offer the lowest static power consumption (<50 microamps) of any programmable device.  


FPGAs offer much higher complexity, up to 150,000 flip-flops, and their idle power consumption is reasonably low, although it is sharply increasing in the newest families.

Because the configuration bitstream must be reloaded every time power is re-applied, design security is an issue, but the benefits and opportunities of dynamic reconfiguration, even in the end-user system, are an important advantage.

FPGAs offer more logic flexibility and more sophisticated system features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and even on-chip microprocessors and Multi-Gigabit Transceivers. 


-- Use CPLDs, especially Cool Runner devices, for small designs, where "instant-on", fast and wide decoding, ultra-low idle power consumption, and design security are important (e.g., in battery-operated equipment). 


For more information on CPLD security, see White Paper WP170: 

-- Use FPGAs for larger and more complex designs.

AR# 7598
Date 02/09/2018
Status Active
Type General Article
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