Since a CLOCK_TO_OUT or a CLOCK_TO_PAD constraint must be relative to a clock pin, you must constrain relative to this clock and adjust your timing value.
For example, suppose you are using a "divide by two" clock internally, and you want to have a CLOCK_TO_OUT constraint of 10 ns. You would constrain relative to the input clock, and double the timing value to 20 ns after a clock edge.
Similarly, if you are using a multiplied clock, you would halve your desired timing value.
For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf