AR# 9410

12.1 Timing Closure - Suggestions for high fanout signals

I placed a timing constraint on a path, but the constraint has errors. What can I do to make this timing constraint pass?

Possible suggestions for high fanout signals:

Floorplan or LOC the origin and the global buffer of the high fanout signal.
Duplicate the driver and tell the synthesis tool not to remove the duplicate logic.
Use specific net fanout control on the specific net, if the synthesis tool allows.

For additional suggestions and recommendations, see the following Answer Records:

Forstate machine optimization, see (Xilinx Answer 9411)
For long carry logic chains, see (Xilinx Answer 9412)
ForI/Os 3-state enable paths, see (Xilinx Answer 9413)
Forpaths through TBUFs, see (Xilinx Answer 9414)
Fortiming through irrelevant paths such as RESET or ".SR" pin, see (Xilinx Answer 9415)
For using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416)
Toavoid having too many levels of logic, see (Xilinx Answer 9417)
For timing constraints that miss their goals by 5% to 10%, see (Xilinx Answer 9418)
For timing constraints that miss their goals by 10% to 15%, see (Xilinx Answer 9419)

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AR# 9410
Date	12/15/2012
Status	Active
Type	General Article
Tools	ISE - 10.1 ISE Design Suite - 11.1 ISE Design Suite - 11.2 More ISE Design Suite - 11.3 ISE Design Suite - 11.4 ISE Design Suite - 11.5 ISE Design Suite - 12.1 ISE Design Suite - 12.2 Less

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