AR# 9410

Description

Solution

• Floorplan or LOC the origin and the global buffer of the high fanout signal.
• Duplicate the driver and tell the synthesis tool not to remove the duplicate logic.
• Use specific net fanout control on the specific net, if the synthesis tool allows.

• Forstate machine optimization, see (Xilinx Answer 9411)
• For long carry logic chains, see (Xilinx Answer 9412)
• ForI/Os 3-state enable paths, see (Xilinx Answer 9413)
• Forpaths through TBUFs, see (Xilinx Answer 9414)
• Fortiming through irrelevant paths such as RESET or ".SR" pin, see (Xilinx Answer 9415)
• For using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416)
• Toavoid having too many levels of logic, see (Xilinx Answer 9417)
• For timing constraints that miss their goals by 5% to 10%, see (Xilinx Answer 9418)
• For timing constraints that miss their goals by 10% to 15%, see (Xilinx Answer 9419)