When a "black box" is instantiated, the following warning occurs:
WARNING: Xst:766 - file_name (Line #). Generating a Black Box for component <component_name>.
A black box is any instantiated component that is not represented by HDL code, but rather by another netlist format.
Synthesis tools will generally report some kind of warning when a black box (an instantiated component with no associated VHDL code) is detected.
Examples of black boxes include:
If you are instantiating a component that is represented by something other than HDL code, no response to the warning message is needed.
If your intent was not to instantiate a black box, check your component declaration and instantiation to ensure that the component is properly represented by HDL code.
To avoid "black box" warning messages, add the following lines to your HDL code:
VHDL:
architecture <architecture_name>
:
attribute box_type : string;
attribute box_type of <component_name> : component is "black_box";
:
begin
Verilog:
//synthesis attribute box_type <module_name> "black_box"
| AR# 9838 | |
|---|---|
| Date | 09/12/2014 |
| Status | Active |
| Type | General Article |
| Tools |
|