Course Listing

Courses are categorized by design specialization:

FPGA design
Connectivity design
DSP design
Embedded design
CPLD design

For tuition and registration information as well as class schedules, please contact one of our Authorized Training Providers.

FPGA Design Courses

Fundamentals of FPGA Design

Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.

Designing for Performance

Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

Advanced FPGA Implementation

Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE 10.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 10.1 tools and the Virtex®-5 and Spartan®-3E FPGAs.

Designing with the PlanAhead Analysis and Design Tool

Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software tool. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.

Designing with the Virtex-4 Family

Learn how to utilize Virtex-4 FPGA architectural resources effectively. This course includes an overview of the Virtex®-4 FPGA; the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD); global and regional clocking techniques, memory and FIFO; and source synchronous resources. A combination of modules and labs allow for practical hands-on application of the principles taught in this course.

Designing with the Virtex-5 Family

Interested in learning how to effectively utilize Virtex-5 FPGA architectural resources? Targeted towards experienced Xilinx users who have already completed the Fundamentals of FPGA Design and Designing for Performance courses and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device.

Minimizing Your Design Time with the ChipScope Pro Debug and Verification Tools

As FPGA designs become increasingly more complex, designers are searching to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for debug and verification. This one-day course will show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.

Design Techniques for Lower Cost

This course appeals to engineers who have an interest in developing low-cost products, particularly in high-volume markets. The course and exercises cover several different design techniques, which will be interesting and challenging for any digital designer regardless of the final application.

TMRTool

Incoming students with little knowledge of SEU/SET considerations who complete this one-day course will get a thorough overview of how these risks affect technology in general and FPGAs in particular. This introduction to the Xilinx TMR (XTMR) solution addresses designs that require Triple Module Redundancy and provides hands-on experience, allowing you to evaluate TMR’s timing impact, as well as area and pinout considerations. You will also perform design verification to ensure functional integrity for pre- and post-TMR circuits. The XTMR solution incorporates TMRTool, a proprietary software application that offers total control and flexibility for the TMR process for Xilinx FPGAs.

ISE Design Tool Entry

In this course you will learn about project structure, process windows, various ISE software design flows, and Xilinx Synthesis Technology (XST). You will examine XST synthesis and use the XST constraints file in the Project Navigator GUI. You will learn about the Engineering Capture System (ECS) and the State Diagram Editor and ISE Simulator tools.

Introduction to Verilog

This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

Introduction to VHDL

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Advanced VHDL

Increase your VHDL proficiency by learning advanced techniques that help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL. The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.

Connectivity Design Courses

Designing a LogiCORE PCI System

Learn the tips and tricks of PCI design in this two-day course which provides an introduction to basic PCI concepts and architecture as well as intensive training on designing with the PCI core for Xilinx. This course emphasizes and illustrates how PCI transactions take place and gives you an overview of Xilinx PCI solutions. You will learn the basics of Xilinx PCI cores including PCI 64/66 and PCI 32. You will also learn design concepts and basic verification strategies for creating a PCI system design. The labs cover the basic transaction analysis using the ModelSim simulator and the general design flow, from core to verification using ISE 9.1i.

Designing a LogiCORE PCI-X System

This course focuses on the PCI-X Addendum to the PCI Local Bus Specification and provides a detailed examination of the PCI-X LogiCORE™ solution. This course will help digital designers interface the PCI-X LogiCORE solution to a typical user application to create a flexible PCI-X system design.

Designing a LogiCORE PCI Express System

Attending the Designing a LogiCORE PCI Express System course will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system with supporting logic and example designs. With this experience, you can improve your time to market with your PCIe core design.

Designing with Multi-Gigabit Serial I/O

Learn how to employ RocketIO™ GTP serial transceivers in your Virtex-5 LXT FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as CRC, 8B/10B encoding, channel bonding, clock correction, and comma detection. Additional highlighted topics include use of the Architecture Wizard and synthesis and implementation considerations. This course balances lecture modules and practical hands-on labs.

Designing with Ethernet MAC Controllers

After completing this course, you will be familiar with the various Xilinx solutions offering Ethernet connectivity. You will learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. You will also perform simulations and learn to assess hardware design considerations and software development requirements.

Signal Integrity for High-Speed Memory and Processor I/O

Learn how signal integrity techniques are applicable to high-speed interfaces between Xilinx FPGAs and semiconductor memories. This course will teach you about high-speed bus and clock design, including transmission line termination, loading, and jitter. You will work with IBIS models, complete simulations using CAD packages, and manage PCB effects and on-chip termination. This course includes both lecture modules and practical hands-on labs.

DSP Design Courses

Introduction to the AccelDSP Synthesis Tool

Learn how to synthesize an algorithm written in the language of the MATLAB® software into a design that is optimized for a Xilinx FPGA. Find out how to make coding changes in the MATLAB software that improve area and performance. Use the floating-point to fixed-point and design exploration features of the AccelDSP™ synthesis tool to achieve maximum results. Merge a synthesized MATLAB software block into a larger HDL design or System Generator design.

DSP Design Using System Generator

This course allows you to explore the System Generator tool and gain the expertise required to develop advanced, low-cost DSP designs. This intermediate course focuses on using System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification with Xilinx FPGAs.

The MathWorks Simulink for Xilinx

This hands-on The MathWorks course covers the basics of using Simulink, an interactive, graphical environment for modeling and simulating dynamic systems. This course covers all aspects of system modeling with Simulink including creating a model, simulating the system, and analyzing the results. Advanced simulation concepts and simulations from the command line are also explained. The final section discusses refining models by providing additional functionality with S-functions, block masks, and Graphical User Interfaces for interaction with your system. Additional DSP simulation tools and other The MathWorks products are also introduced.

DSP Implementation Techniques for Xilinx FPGAs

This course will show you how to take advantage of Xilinx FPGA architecture, including the Virtex-4 FPGA, to effectively implement DSP algorithms. The techniques also demonstrate which system-level decisions have the greatest impact on the implementation process and product costs.

Embedded Design Courses

Embedded Systems Development

Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.

Advanced Embedded Systems Development

Advanced Features and Techniques of Embedded Systems Development provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Embedded Development Kit (EDK). This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system.

Embedded Systems Software Development

This two-day course introduces you to software design and development for Xilinx embedded processor systems. You will learn the basic tool use and concepts required for the software phase of the design cycle, after the hardware design is completed. Topics are comprehensive, covering the design and implementation of the software platform for resource access and management. Major topics include device driver development and user application debugging and integration. Practical implementation tips and best practices are also provided throughout to enable you to make good design decisions and keep your design cycles to a minimum. You will have enough practical information to get started developing the software platform for a Xilinx embedded system based on a PowerPC 440 or MicroBlaze processor.

Embedded Open-Source Linux Development

This intermediate-level, two-day course provides embedded systems developers with experience in creating an embedded open-source Linux operating system on a Xilinx development board. The course offers students hands-on experience from building the environment to booting the system using a basic, single-processor System on Chip (SoC) design with Linux 2.6 from the Xilinx kernel tree. This course introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging/profiling options for embedded Linux platforms. The primary focus is on embedded Linux development in conjunction with the Xilinx tool flow

CPLD Design Courses

Fundamentals of CPLD Design

This comprehensive course provides you with an introduction to designing with Xilinx CPLDs by using the ISE series software tools. You will learn the basics of ISE software flow and how to interpret CPLD reports for optimum performance designs. This course covers ISE features such as the Constraints Editor and PACE. Other topics include design planning, implementation options, and global timing constraints. You will ultimately configure a CPLD demo board by using Xilinx configuration software.

Designing for Performance for CPLDs

Designing for Performance for CPLDs is an intermediate-level course that provides a comprehensive overview of the CPLD software flow. By applying the techniques presented in this course, you will be able to enhance design performance and make the best possible use of Xilinx CPLD architectures. This course uses the ISE 9.1 software, including the Constraints Editor and Timing Analyzer. Other topics include understanding the CPLD logic engine, estimating power, and fitting difficult designs.