UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

  • Program Tier: Member

EASYIC DESIGN SRL

  • Program Member Since: 2017
  • Certified Engineers: 1
    • Bucharest, RO (Headquarters)

Partner Information

EasyIC Design is an IC design services and Verification IP company based in Bucharest, Romania. EasyIC has extensive IC development experience gained from working on successful projects with leading semiconductor and systems companies. Its expertise includes digital design and verification using industry standard methodologies and languages such as SystemVerilog and UVM. EasyIC also has expertise in the customized application of these methodologies to the top-level verification of Mixed Signal chips.

Internally, EasyIC has developed a library of synthesizable Bus Functional Models (sBFM) for full chip and system validation. These fully synthesizable BFMs can be used on industry emulation platforms and on FPGA based platforms such as Xilinx Virtex® UltraScale™ modules. The library includes memory models for DDR3, LPDDR3, DDR4 and LPDDR4. Memory expansion of the models can be achieved by the use of the EasyIC SRAM to Xilinx MIG Bridge. EasyIC is currently expanding the library to Ethernet sBFMS including Ethernet for Automotive. EasyIC also offers custom sBFM development to its clients for standard and proprietary protocols. All sBFMs have been developed using SystemVerilog and a complete UVM based testbench is also available for each sBFM.

Products/Services

  • Design Services
  • IP Cores

Markets Supported

  • Audio Video and Broadcast
  • Automotive
  • Consumer Electronics
  • Data Center
  • Industrial
  • Medical
  • Wired Communications
  • Wireless Communications

Design Competencies

  • Computer Vision
  • Digital Signal Processing
  • Embedded Application Development
  • Embedded Processors
  • FPGA Design and Integration
  • FPGA Design Optimization
  • FPGA Timing Closure
  • RF and Analog Design
  • Signal Integrity Design and Analysis
  • System Architecture

Maximum Service Scope

  • System Level Design

Engagement Model

  • Time and Materials
  • SOW-Based Fixed Bid Projects
  • Captive Engineering Resources at Partner and Customer Location
Page Bookmarked