Xilinx FPGAs, SoCs, MPSoCs, and ACAPs support many different memory technologies internal or external to the device. With programmable logic often being used as accelerators in processing platforms, many Xilinx devices support all cache coherent interfaces including the CCIX open standard and CXL.
Versal™ ACAP | UltraScale+ | UltraScale™ | 7 Series | Spartan®-6 | |
---|---|---|---|---|---|
Block RAM | 174Mb | 94Mb | 36Kb | 50Mb | 4Mb |
UltraRAM | 717Mb | 360Mb | – | – | – |
High Bandwidth Memory | 32GB | 16GB | – | – | – |
External Max Data Rate | 4266Mb/s | 2667Mb/s | 2400Mb/s | 1866Mb/s | 800Mb/s |
Xilinx products contain different types of internal memory for different design needs.
Versal™ ACAP | UltraScale+™ | UltraScale™ | 7 Series | Spartan®-6 | |
---|---|---|---|---|---|
Distributed RAM size | 64-bit | 64-bit | 64-bit | 64-bit | 64-bit |
Distributed RAM capacity range | 0.6 – 103Mb | 1.2Mb – 48.3Mb | 4.1Mb – 28.7Mb | 70Kb – 21Mb | 75Kb – 1.3Mb |
Block RAM size | 36Kb | 36Kb | 36Kb | 36Kb | 18Kb |
Block RAM capacity range | 0.8Mb – 174Mb | 5.3Mb – 94.5Mb | 12.7 – 132.9Mb | 180Kb – 66.1Mb | 216Kb – 4.7Mb |
UltraRAM size | 288Kb | 288Kb | – | – | – |
UltraRAM capacity range | 6.8Mb – 717Mb | 90Mb – 360Mb | – | – | – |
HBM size | 8GB – 16GB | 4GB – 8GB | – | – | – |
HBM capacity range | 8GB – 32GB | 4GB – 16GB | – | – | – |
Xilinx offers a comprehensive set of physical layer memory interfaces and memory controllers for varied bandwidth, efficiency, and low latency requirements. Based on a rigorous characterization process to determine specifications, interface supports include DDR3 and DDR4 multi-rank DIMMs, including UDIMM, SODIMM, and RDIMM with DQS groups of x4 and x8. Refer to the following tools to plan your memory interface design and implementation:
Xilinx memory controllers are included in the Vivado® IP Catalog at no extra charge.
Max Bandwidth (Mb/s) | |||||
---|---|---|---|---|---|
Speed Grade | -1 | -2 | -3 | ||
Temp Grade | LI | I/E | LE | I/LE | E |
VCCINT | 0.72V | 0.85V | 0.72V | 0.85V | 0.90V |
DDR4 HP I/O | 2133 | 2400 | 2400 | 2666 | 2666 |
DDR3 HP I/O | 1866 | 2133 | 2133 | 2133 | 2133 |
DDR3L HP I/O | 1600 | 1866 | 1866 | 1866 | 1866 |
LPDDR3 HP I/O | 1600 | 1600 | 1600 | 1600 | 1600 |
QDR-II+ (MHz) HP I/O | 550 | 600 | 600 | 633 | 633 |
QDR-IV XP (MHz) HP I/O | 933 | 1066 | 933 | 1066 | 1066 |
RLDRAM 3 (MHz) HP I/O | 933 | 1066 | 1066 | 1200 | 1200 |
HMC Gen 2 | 15000TX + 15000RX |
15000TX + 15000RX |
15000TX + 15000RX |
15000TX + 15000RX |
15000TX + 15000RX |
Bandwidth Engine 3 | 10313 | 10312 | 28000 | 28000 | 28000 |
Bandwidth Engine 2 | 10313 | 10313 | 10313 | 15500 | 15500 |
Zynq® UltraScale+™ MPSoCs have a hard memory controller in the processing system. These devices can support 32GB of addressable memory. Additional memory can be added in the programmable logic region.
Max Bandwidth (Mb/s) | |||
---|---|---|---|
Interface | -1 | -2 | -3 |
DDR4 Component | 2400 | 2400 | 2400 |
LPDDR4 Component | 2400 | 2400 | 2400 |
DDR3 Component | 2133 | 2133 | 2133 |
DDR3L Component | 1866 | 1866 | 1866 |
LPDDR3 Component | 1600 | 1600 | 1600 |
Max Bandwidth (Mb/s) | |||||||
---|---|---|---|---|---|---|---|
Interface | Bank Type | Package | -1LI Vccint = 0.72V |
-2LE Vccint = 0.72V |
-1 Vccint = 0.85V |
-2 Vccint = 0.85V |
-3 Vccint = 0.95V |
DDR4 Component | HP | FFV/FLV | 2133 | 2400 | 2400 | 2666 | 2666 |
DDR4 Component | HP | FBVA676 | 1600 | 1866 | 1866 | 2133 | 2133 |
DDR4 DIMM 1R | HP | All | 1866 | 2133 | 2133 | 2400 | 2400 |
DDR4 DIMM 2R | HP | All | 1600 | 1866 | 1866 | 2133 | 2133 |
DDR4 DIMM 4R | HP | All | N/A | 1333 | 1333 | 1600 | 1600 |
DDR3 Component | HP | FFV/FLV | 1866 | 2133 | 2133 | 2133 | 2133 |
DDR3 DIMM 1R | HP | All | 1600 | 1866 | 1866 | 1866 | 1866 |
DDR3 DIMM 2R | HP | All | 1333 | 1600 | 1600 | 1600 | 1600 |
DDR3 DIMM 4R | HP | All | 800 | 1066 | 1066 | 1066 | 1066 |
DDR3L Component | HP | FFV/FLV | 1600 | 1866 | 1866 | 1866 | 1866 |
RLDRAM 3 (MHz) | HP | 933 | 1066 | 1066 | 1200 | 1200 | |
QDR-IV (MHz) | HP | All | 933 | 933 | 1066 | 1066 | 1066 |
HMC Gen 2 | GT | All | 15000TX + 15000RX |
15000TX + 15000RX |
15000TX + 15000RX |
15000TX + 15000RX |
15000TX + 15000RX |
Bandwidth Engine 3 | GTY | All | 10313 | 28000 | 10312 | 28000 | 28000 |
Bandwidth Engine 2 | GTH | All | 10313 | 10313 | 10313 | 15500 | 15500 |
Max Bandwidth (Mb/s) | ||||
---|---|---|---|---|
Speed Grade | -1 | -2 | -3 | |
Temp Grade | C/I/LI/HE | HE | E/I | E |
VCCINT | 0.95V | 1.0V | 0.95V | 1.0V |
DDR4 HP I/O | 2133 | 2400 | 2400 | 2400 |
DDR3 HP I/O | 1866 | 2133 | 2133 | 2133 |
DDR3L HP I/O | 1600 | 1866 | 1866 | 1866 |
QDR-II+ (MHz) HP I/O | 550 | 600 | 600 | 633 |
QDR-IV (MHz) HP I/O | 667 | 800 | 800 | 800 |
RLDRAM 3 (MHz) HP I/O | 933 | 1066 | 1066 | 1066 |
HMC Gen 2 | 15000TX + 15000RX |
15000TX + 15000RX |
15000TX + 15000RX |
15000TX + 15000RX |
Bandwidth Engine 3 | 10313 | 15500 | 28000 | 28000 |
Bandwidth Engine 2 | 10313 | 15500 | 15500 | 15500 |
Zynq-7000 programmable SoCs have a hard memory controller in the processing system. Zynq-7000 SoCs can support 1GB of addressable memory. Additional memory can be added in the programmable logic region.
Max Bandwidth (Mb/s) | |||
---|---|---|---|
Interface | -1 | -2 | -3* |
DDR3 Component | 1066 | 1066 | 1066 |
DDR3L Component | 1066 | 1066 | 1066 |
DDR2 Component | 800 | 800 | 800 |
LPDDR2 Component | 800 | 800 | 800 |
* -3 Speed grade not available in Z-7007S, Z-7012S, and Z-7014S
Max Bandwidth (Mb/s) | |||
---|---|---|---|
Interface | -1 | -2 | -3 |
DDR3 Component | 1066 | 1066 | 1333 |
DDR3L Component | 1066 | 1066 | 1066 |
DDR2 Component | 800 | 800 | 800 |
LPDDR2 Component | 800 | 800 | 800 |
Max Bandwidth (Mb/s) | |||
---|---|---|---|
Vccint = 1.0V | |||
Interface | -1 | -2 | -3* |
DDR3 Component | 800 | 800 | 1066 |
DDR3L Component | 667 | 800 | 800 |
DDR2 Component | 667 | 800 | 800 |
LPDDR2 Component | 533 | 667 | 667 |
* -3 Speed grade not available in Z-7007S, Z-7012S, and Z-7014S
Max Bandwidth (Mb/s) | ||||||
---|---|---|---|---|---|---|
Vccint = 0.95V | Vccint = 1.0V | |||||
Interface | Bank Type | Vccaux_IO | -2LI | -1 | -2 | -3E |
DDR3 Component | HP | 2.0V | 1600 | 1600 | 1866* | 1866* |
DDR3 Component | HP | 1.8V | 1333 | 1066 | 1333 | 1600 |
DDR3 Component | HR | N/A | 1066 | 800 | 1066 | 1066 |
DDR3L Component | HP | 2.0V | 1600 | 1333 | 1600 | 1600 |
DDR3L Component | HP | 1.8V | 1066 | 800 | 1066 | 1333 |
DDR3L Component | HR | N/A | 800 | 667 | 800 | 800 |
QDR-II+ (MHz) | HP | All | 1000 | 900 | 1000 | 1100 |
QDR-II+ (MHz) | HR | N/A | 900 | 800 | 900 | 1000 |
RLDRAM II (MHz) | HP | All | 1000 | 900 | 1000 | 1066 |
RLDRAM II (MHz) | HR | N/A | N/A | N/A | N/A | N/A |
Bandwidth Engine 3 | GTH | N/A | 10313 | N/A | 10313 | 10313 |
Bandwidth Engine 2 | GTH | N/A | 10313 | N/A | 10313 | 10313 |
Max Bandwidth (Mb/s) | |||||||
---|---|---|---|---|---|---|---|
Interface | Bank Type | Vccaux_IO | -2LE Vccint = 0.9V |
-2LI Vccint = 0.95V |
-1 Vccint= 1.0V |
-2 Vccint = 1.0V |
-3 Vccint = 1.0V |
DDR3 Component | HP | 2.0V | 1333 | 1600 | 1600 | 1866* | 1866* |
DDR3 Component | HP | 1.8V | 1066 | 1333 | 1066 | 1333 | 1600 |
DDR3 Component | HR | N/A | 800 | 1066 | 800 | 1066 | 1066 |
DDR3L Component | HP | 2.0V | 1066 | 1600 | 1333 | 1600 | 1600 |
DDR3L Component | HP | 1.8V | 800 | 1066 | 800 | 1066 | 1333 |
DDR3L Component | HR | N/A | 667 | 800 | 667 | 800 | 800 |
QDR-II+ (MHz) | HP | All | 900 | 1000 | 900 | 1000 | 1100 |
QDR-II+ (MHz) | HR | N/A | 800 | 900 | 800 | 900 | 1000 |
RLDRAM II (MHz) | HP | All | 900 | 1000 | 900 | 1000 | 1066 |
RLDRAM II (MHz) | HR | N/A | N/A | N/A | N/A | N/A | N/A |
Bandwidth Engine 3 | GTH | N/A | N/A | 10313 | N/A | 10313 | 10313 |
Bandwidth Engine 2 | GTH | N/A | N/A | 10313 | N/A | 10313 | 10313 |
*For designs that require > 1800 Mb/s, open a webcase with Xilinx Technical Support
Max Bandwidth (Mb/s) | |||||
---|---|---|---|---|---|
Interface | -2LE Vccint = 0.9V |
-1LI Vccint = 0.95V |
-1 Vccint= 1.0V |
-2 Vccint = 1.0V |
-3 Vccint = 1.0V |
DDR3 Component | 800 | 800 | 800 | 800 | 1066 |
DDR3L Component | 667 | 667 | 667 | 800 | 800 |
DDR2 Component | 667 | 667 | 667 | 800 | 800 |
LPDDR2 Component | 533 | 533 | 533 | 667 | 667 |
Max Bandwidth (Mb/s) | |||
---|---|---|---|
Interface | -1LI Vccint = 0.95V |
-1 Vccint= 1.0V |
-2 Vccint = 1.0V |
DDR3 Component | 667 | 667 | 800 |
DDR3L Component | 667 | 667 | 800 |
DDR2 Component | 667 | 667 | 800 |
LPDDR2 Component | 533 | 533 | 667 |
Memory Type | ||||
---|---|---|---|---|
DDR3 SDRAM | DDR2 SDRAM | DDR SDRAM | LPDDR SDRAM | |
Spartan-6 | 800 Mb/s | 800 Mb/s | 400 Mb/s | 400 Mb/s |
Xilinx provides best-in-class tools to estimate memory performance, interface capacity, and power consumption to maximize performance-per-watt and accelerate design and implementation. Below are a variety of memory- and power-related tools to get started today.
Relative Merit | DDR4 DIMM | HMC | RLDRAM 3 | QDR-IV | LPDDR4 | Virtex® UltraScale+™ HBM Device | Versal™ HBM ACAP |
---|---|---|---|---|---|---|---|
Bandwidth | 21GB/s | 160GB/s | 10.8GB/s | 16.8GB/s | 9.6GB/s | 460GB/s | 820GB/s |
Density | 32GB | 2GB | 280MB (0.280GB) |
18MB (0.018GB) |
4GB | 16GB | 32GB |
Price / GB | $ | $$$ | $$ | $$ | $$ | $$ | $$ |
PCB Requirement | High | Medium | High | High | High |
None | None |
Power (pJ/bit) | ~27 | ~30 | ~40 | ~27 | ~19 | ~7 | ~6 |
Latency | Med | High | Low | Low | Med | Med | Med |