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Vitis Unified Software Platform 2022.1 Release Highlights :

Vitis Unified Software Platform 2022.1 now available

Vitis™ flow enhancement for Versal® ACAP and AI Engine

• Supports XIlinx base DFX platform with one static region and one DFX region
• AIE profiling supports stall/deadlock detection, generates AI Engine status (including error events) view reports​ in Vitis Analyzer
• External Traffic Generators in x86sim, AIEsim, and SW emulation are much more flexible and can be inserted very easily in Simulation and Emulation flows
• Vitis Model Composer supports Hardware Validation, Linux and HW emulation

Vitis for DC and Vitis HLS

• Vitis Provides additional reporting support for the dynamic region generation process and Flow reporting enhancements include 3 new or updated reports
• Vitis Improves PL profiling with the choice of offloading trace to memory resources (preferred) or FIFO in the PL for better performance
• A new Timeline Trace Viewer to show the runtime profile and allows user to remain in the Vitis HLS GUI is now available after simulation
• Vitis HLS now supports a higher level type of "smart" construct via the new performance pragma or the set_performance_directive
• Vitis Graph Library with L3 API enhancements for performance

Note:

• To install Vitis Core Development Kit, select Vitis on the Xilinx Unified Installer. Vitis installation includes Vivado® Design Suite, Vitis Model Composer, Vitis HLS.

       
             – There is no need to install Vivado separately.