New Vitis™ Library Functions for Versal™ AI Engine (AIE) Arrays
Design Flow Enhancements for Versal AI Core and AI Edge Series
Support for Vitis environment export to the Vivado™ environment
Expand the sections below to learn more about the new features and enhancements in Vitis software platform 2023.1. For information on supported platforms, changed behavior, and known issues, please refer to the Vitis software platform 2023.1 Release Notes for the Application Acceleration Flow and Embedded Software Development Flow.
DSP Library - FIR Filters
Solver Library
Footnotes:
*The benchmark tests were performed on all 1208 Vitis L1 library C-code designs as of February 12th, 2023. All designs were run using a system with 2P Intel Xeon E5-2690 CPUs with CentOS Linux, SMT enabled, Turbo Boost disabled. Hardware configuration not expected to effect software test results. Results may vary based on software and firmware settings and configurations- VGL-03
New Vitis™ Library Functions for Versal™ AI Engine (AIE) Arrays
Design Flow Enhancements for Versal AI Core and AI Edge Series
Expand the sections below to learn more about the new features and enhancements in Vitis software platform 2022.2. For information on supported platforms, changed behavior and known issues, please refer to the Vitis software platform 2022.2 Release Notes for Application Acceleration Flow and Embedded Software Development Flow.
DSP library functions
Solver library functions
Vision library functions
Ultrasound library functions
Vitis environment 2022.2 new simulation options: Processor system x86 simulation and AI Engine x86 simulation: Programmable logic simulation can be performed using the x86 simulator.
Features for Versal AI Engine Design
General Features
Vitis™ Flow Enhancement for Versal™ ACAP and AI Engine
Vitis for DC and Vitis HLS
Expand the sections below to learn more about the new features and enhancements in Vitis 2022.1. For information on Supported Platforms, Changed Behavior & Known Issues, please refer to Vitis 2022.1 Release Notes for Application Acceleration Flow and Embedded Software Development Flow.
Expand the sections below to learn more about the new features and enhancements in Vitis 2021.2. For information on Supported Platforms, Changed Behavior & Known Issues, please refer to Vitis 2021.2 Release Notes for Application Acceleration Flow and Embedded Software Development Flow.
Note: Vitis Accelerated Libraries are available as a separate download. They can be downloaded from GitHub or directly from within the Vitis IDE as well.
Library | 2021.1 | 2021.2 | New functions in 21.2 |
---|---|---|---|
xf_blas | 167 | 167 | 0 |
xf_codec | 3 | 3 | 0 |
xf_DataAnalytics | 33 | 36 | 3 |
xf_database | 62 | 65 | 3 |
xf_compression | 78 | 93 | 15 |
xf_dsp | 94 | 96 | 2 |
xf_graph | 53 | 59 | 6 |
xf_hpc | 37 | 37 | 0 |
xf_fintech | 116 | 116 | 0 |
xf_security | 135 | 140 | 5 |
xf_solver | 11 | 11 | 0 |
xf_sparse | 11 | 11 | 0 |
xf_utils_hw | 55 | 57 | 2 |
xf_opencv | 147 | 150 | 3 |
total | 1002 | 1041 | 39 |
Note: For vision, just count the number of sub folders in L*/tests, because each API has multiple tests for different types
Programmable Logic (PL)
New Features | Cat | Customer/Strategic | Segments | Description |
---|---|---|---|---|
RGB-IR | ISP | Seeing Machines | Automotive, ISM | •Support 4x4 RGB-IR demosaicking •Primarily for in-cabin monitoring system •Low light surveillance camera |
Mono (CCCC) | ISP | Strategic | Automotive, ISM, A&D | •Machine vision •Low light applications |
Global Tone Mapping (GTM) | ISP | Strategic | Automotive, ISM, A&D | •Improved dynamic range and contrast •Lower cost version compared to local tone mapping (LTM) |
Dense Optical Flow TV-L1 | CV | NTT | ISM | •Improved robustness (against illumination, noise, occlusions) for optical flow |
AI Engine (AIE)
New Features | Cat | Customer/Strategic | Segments | Description |
---|---|---|---|---|
RGB-IR | ISP | Seeing Machines | Automotive, ISM | •Support 4x4 RGB-IR demosaicking •Primarily for in-cabin monitoring system •Low light surveillance camera |
ML+X | ISP | Strategic | Automotive, ISM, A&D | •ML interference pre-processing |
Gaussian Pyramid | CV | Strategic | Automotive, ISM, A&D | •Fundamental for multi-scale image processing |
Box Filter | CV | Strategic | Automotive, ISM, A&D | •Fundamental for smoothing, low pass filter |
Vitis Blockchain Solution based on Vitis libraries
Adding CSV parser API into library
KECCAK-256 (hash function) and CRC32C (checksum function) are released
Two Data-Mover implementation are added for debugging hw issue.
AI Engine API will be the lead method for AI Engine kernel programming
AI Engine compiler optimization options
Introducing --xlopt=2 to improve performance, default remains --xlopt=1
Necessary for optimizing the kernels
Support to auto-infer five pragmas in 2021.2
Model Changes Include:
Current
GMIO gm0(“GMIO_In0”, 64, 1);
GMIO gm1(“GMIO_In1”, 64, 1);
…
GMIO gm7(“GMIO_In7”, 64, 1);
PLIO pl0(“PLIO_Out0”, plio_32_bits, “data/output0.txt”, 250.0);
PLIO pl1(“PLIO_Out1”, plio_32_bits, “data/output1.txt”, 250.0);
…
PLIO pl7(“PLIO_Out7”, plio_32_bits, “data/output7.txt”, 250.0);
simulation::platform<8,8> plat(&gm0, &gm1,…, &gm7, &pl0, &pl1,…, &pl7,);
subgraph g;
connect<> net0(plat.src[0], g.in[0]);
connect<> net1(plat.src[1], g.in[1]);
…
connect<> net7(plat.src[7], g.in[7]);
connect<> net8(g.out[0], plat.sink[0]);
connect<> net9(g.out[1], plat.sink[1]);
…
connect<> net15(g.out[7], plat.sink[7]);
Alternative method
class topgraph
{
input_gmio gm[8];
output_plio pl[8];
subgraph sg;
topgraph()
{
for (i=0; i<8; i++)
{
gm[i] = input_gmio::create(“GMIO_In”+std::to_string(i), 64, 1);
pl[i] = output_plio::create(“PLIO_Out”+std::to_string(i), plio_32_bits, “data/output”+std::to_string(i)+”.txt”, 250.0);
connect<>(gm[i].out[0], sg.in[i]);
connect<>(sg.out[i], pl[i].in[0]);
}
}
};
topgraph g;
Ability to use flags in the ADF graph or constraints file to control the mapper and router
Snapshots are textfiles containing comments and data relative to all kernel ports
Includes also all platform ports
Allows users to inspect data traffic at kernel ports without using the debugger and without requiring instrumentation of kernel code
Integration with Valgrind for Memory Access Violation Detection
Deadlock situation results in poor simulation output and difficulties to analyze bug origin
X86 simulation trace option allows the simulator to log various timestamped information:
Timestamps are different in between x86 simulation and AI Engine simulation
Add interface adaptors report in the C synthesis reports
Add new section in synthesis report to show list of pragmas and warnings on pragmas
The Function Call Graph Viewer has some new features
A new Timeline Trace Viewer is now available after simulation. This viewer shows the runtime profile of your design and allows the user to remain in the Vitis HLS GUI.
AI Engine application emulation enhancements
Support AI Engine Trace
Support SW Emulation for AI Engine applications
Support external traffic generator in Verilog / System Verilog
Generic profile summary report generated for non-OpenCL applications
Add OpenCL commands to PL event timeline
Flatten signal hierarchy in timeline trace report
C and C++ APIs
enum class access_mode : uint8_t { exclusive = 0, primary = 1, shared = 2 };
enum class access_mode : uint8_t { exclusive = 0, primary = 1, shared = 2, none = 3 };
Access latest Vitis Target Platforms for Alveo Cards:
Refer to UG1120 - Alveo Data Center Accelerator Card Platforms User Guide
Reduced times vs. 2021.1 (As an example, the following numbers are for the 200 MHz TX Chain):
Expand the sections below to learn more about the new features and enhancements in Vitis 2021.1. For information on Supported Platforms, Changed Behavior & Known Issues, please refer to Vitis 2021.1 Release Notes for Application Acceleration Flow and Embedded Software Development Flow.
Note: Vitis Accelerated Libraries are available as a separate download. They can be downloaded from GitHub or directly from within the Vitis IDE as well.
FIR Filters
Function |
Namespace |
Single rate, asymmetrical |
dsplib::fir::sr_asym::fir_sr_asym_graph |
Single rate, symmetrical |
dsplib::fir::sr_sym::fir_sr_sym_graph |
Interpolation asymmetrical |
dsplib::fir::interpolate_asym::fir_interpolate_asym_graph |
Decimation, halfband |
dsplib::fir::decimate_hb::fir_decimate_hb_graph |
Interpolation, halfband |
dsplib::fir::interpolate_hb::fir_interpolate_hb_graph |
Decimation, asymmetric |
dsplib::fir::decimate_asym::fir_decimate_asym_graph |
Interpolation, fractional, asymmetric |
dsplib::fir::interpolate_fract_asym:: fir_interpolate_fract_asym_graph |
Decimation, symmetric |
dsplib::fir::decimate_sym::fir_decimate_sym_graph |
FFT/iFFT - The DSPLib contains one FFT/iFFT solution. This is a single channel, single kernel decimation in time, (DIT), implementation with configurable point size, complex data types, cascade length and FFT/iFFT function.
Function |
Namespace |
Single Channel FFT/iFFT |
dsplib::fft::fft_ifft_dit_1ch_graph |
Matrix Multiply (GeMM) - The DSPLib contains one Matrix Multiply/GEMM (GEneral Matrix Multiply) solution. This supports the Matrix Multiplication of 2 Matrices A and B with configurable input data types resulting in a derived output data type.
Function |
Namespace |
Matrix Mult / GeMM |
dsplib::blas::matrix_mult::matrix_mult_graph |
Widget Utilities - These widgets support converting between window and streams on the input to the DSPLib function and between streams to windows on the output of the DSPLib function where desired and additional widget for converting between real and complex data-types.
Function |
Namespace |
Stream to Window / Window to Stream |
dsplib::widget::api_cast::widget_api_cast_graph |
Real to Complex / Complex to Real |
dsplib:widget::real2complex::widget_real2complex_graph |
Vitis HPC Library release introduces HLS primitives, prebuild kernles and software APIs for HPC applications on FPGAs. These applications are:
2D Acoustic RTM (Reverse Time Migration) FDTD (Finite Difference Time Domain) algorithm, including forward kernel and backward kernel
3D Acoustic RTM (Reverse Time Migration) FDTD (Finite Difference Time Domain) algorithm, including forward kernel
MLP (Mult-Layer Perceptron) components: activation functions and fully connected network kernels
PCG (Preconditioned Conjugate Gradient) Solvers for both dense matrix and sparse matrix
Functions available
Filter2D
absdiff
accumulate
accumulate_weighted
addweighted
blobFromImage
colorconversion
convertscaleabs
erode
gaincontrol
gaussian
laplacian
pixelwise_mul
threshold
zero
xfcvDataMovers : Utility datamovers to facilitate easy tiling of high resolution images and transfer to local memory of AI Engines cores. Two flavors
Library Related Changes
The 2021.1 release provide Two-Gram text analytics:
Two Gram Predicate (TGP) is a search of the inverted index with a term of 2 characters. For a dataset that established an inverted index, it can find the matching id in each record in the inverted index.
In 2021.1 release, GQE receives early-access support the following features
64-bit join support: now the gqeJoin kernel and its companion gqePart kernel has been extended to 64-bit key and payload, so that a larger scale of data can be supported.
Initial Bloom-filter support: the gqeJoin kernel now ships with a mode in which it executes Bloom-filter probing. This improves efficiency on certain multi-node flows where minimizing data size in the early stage is important.
Both features are offered now as L3 pure software APIs, please check corresponding L3 test cases.
XRT managed kernel is the default flow.
Support encrypted AIE source files as input
AIE compiler can accept encrypted AIE source file and v++ supports the rest of the flow.
Vitis Analyzer shows a critical timing path.
Vitis Analyzer will display a simplified version of the Vivado GUI timing report, without the need to open a Vivado project or netlist. This allows users to quickly navigate to the failing timing path.
Vitis Analyzer multiple strategies support
Results from multiple strategies run can be visualized in Vitis Analyzer.
Reduce memory and loading time for large applications
The new profile tool takes less resource for processing large csv file, which reduces the loading time and the crashing problem occurrence.
PL continuous trace offloading improvement
Use DDR or HBM as memory resource to store trace data
Circular buffer support for large data offloading
Trace buffer size and offloading interval can be set in xrt.ini
Improvements to the visualization of AIE design’s trace report
All AIE inputs will be displayed(window, stream, cascaded stream, etc.)
Support all IO data types
Access the latest Vitis Target Platforms for Alveo Accelerator cards at www.xilinx.com/alveo. Please refer to the Getting Started section of the accelerator card you want to deploy your applications on.
Please refer to UG1120 - Alveo Data Center Accelerator Card Platforms User Guide for more details and to keep up-to-date on the latest Vitis Target Platform releases, as they become available.
New Platforms
Expand the sections below to learn more about the new features and enhancements in Vitis 2020.2. For information on Supported Platforms, Changed Behavior & Known Issues, please refer to Vitis 2020.2 Release Notes for Application Acceleration Flow and Embedded Software Development Flow.
Note: Vitis Accelerated Libraries are available as a separate download. They can be downloaded from GitHub or directly from within the Vitis IDE as well.
New Functions and Features
Library Infrastructure & Other Enhancements
Ready-to-Evaluate Apps in New AMD App Store
The following FPGA-accelerated applications, developed using the Vitis Vision library, are now available on the new AMD App Store as containers for easy evaluation and deployment on Alveo accelerator cards on the Nimbix cloud or On-premise
Versal Only Features
Versal Only Features
Versal Only Features
Versal Only Features
Versal Only Features
Note: Xilinx Runtime Library (XRT) is available as a separate download. Please refer to the Getting Started information for download and install instructions.
Versal Only Features
Access the latest Vitis Target Platforms for Alveo Accelerator cards from the Alveo Packages Download Tab
Please refer to UG1120 - Alveo Data Center Accelerator Card Platforms User Guide for more details and to keep up-to-date on the latest Vitis Target Platform releases, as they become available
U200/U250 XDMA Platforms
Shell Upgrade DFX - 2RP ( 2 Reconfiguration Partitions)
AXI Slave Bridge
Data Retention - DDR4 self-refresh
Note: Vitis Target Platforms for Embedded Platforms (including pre-built linux kernels, root file system and sysroot) are available as a separate download on Vitis Embedded Platforms Tab
The VCK190 platform has flexible DDR + LPDDR memory subsystem and supports 63 interrupts for acceleration kernels. It is available for use with the Vitis core development kit, for both application acceleration and embedded processor software development, as described in Versal AI Engine Programmers Guide (UG1076). The platform enables development of designs that include: