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Power Efficiency

Unrivaled System-level Power Reduction

Overview

Through careful selection of silicon process and power-conscious architecture design, AMD Xilinx devices deliver power efficiency across all product portfolios, including adaptive compute acceleration platform (ACAP) devices, Spartan®-6 FPGAs, 7 series FPGAs, UltraScale™ FPGAs, UltraScale+™ FPGAs, and adaptive SoCs. With each generation, AMD Xilinx broadens its power-reduction capabilities, ranging from process enhancements, architectural innovations, aggressive voltage scaling, and advanced software optimization strategies. More details on portfolio-specific capabilities, silicon process advantages, and benchmark comparisons are shown below. Power estimation, thermal models, full software support, and demonstration boards are publicly available for all families. Designing power for AMD Xilinx devices is easier than ever before with comprehensive documentation, built and tested power reference designs, and powerful tools to unlock the potential of your next design to get the most out of your ACAP, SoC, or FPGA.

Versal ACAP

The Versal® ACAP is the next-generation, heterogeneous compute device built on TSMC’s 7nm HK-MG FinFET process, taking the next leap in low-power and high-performance technology through architectural innovation and power-optimized blocks. The Versal AI Engine architecture delivers up to 40% power savings for compute-intensive 

  • Hardened block RAM, UltraRAM, and DSP blocks improve device efficiency
  • More efficient DSP blocks for enhanced complex and floating-point math operations
  • Unused block RAMs support power gating to avoid power leakage
  • UltraRAM initialization and width configurability reduce the need for external RAM/ROM

The combination of Versal ACAP hardened and programmable blocks allows designers to maximize performance per watt by including previous generation power-saving techniques, as well as improved power management, new voltage and frequency scaling, and integrated system monitoring for board-level, intelligent power management.

UltraScale+ FPGAs

Built on TSMC’s 16nm FinFET+ high-performance, low-power semiconductor process, the UltraScale+ device families deliver up to 60% overall device-level power savings over 7 series FPGAs and SoCs. Architectural enhancements include:

  • Hardware-based clock gating
  • Hardened block RAM cascading
  • DSP block efficiencies
  • Power-optimized transceivers

Through architectural innovation and dual-voltage operation of the primary core fabric, UltraScale+ families more than double the performance per watt capabilities of 7 series families by realizing power reductions while improving overall performance.

UltraScale+ FPGA power savings

  7 Series
(28nm)
VNOM
UltraScale
(20nm)
VNOM
UltraScale+
(16nm)
VNOM
UltraScale+
(16nm)
VLOW
Operating Voltage (VCCINT) 1V 0.95V 0.85V 0.72V
Normalized Facric Performance 1.0x 1.2x 1.6x 1.2x
Normalized Total Power 1.0x 0.7x 0.8x 0.5x
Performance/Watt 1.0x 1.7x 2x 2.4x

Zynq UltraScale+ MPSoCs

In addition to all the power reducing capabilities of UltraScale+ FPGA logic, Zynq® UltraScale+ MPSoCs utilize multiple power islands and domains within the processing system for coarse-grain and fine-grain dynamic power gating to continually adjust power consumption to performance demands—lowering overall device power.

UltraScale FPGAs

Built on TSMC’s low-power 20nm semiconductor process coupled with significant static and power gating, UltraScale FPGA families deliver up to 40% overall device-level power savings compared to 7 series FPGAs. Architectural enhancements shared with UltraScale+ devices include:

  • Hardware-based clock gating
  • Hardened block RAM cascading
  • DSP block efficiencies
  • Power-optimized transceivers

UltraScale power savings

  7 Series
(28nm)
VNOM
UltraScale
(20nm)
VNOM
UltraScale+
(16nm)
VNOM
UltraScale+
(16nm)
VLOW
Operating Voltage (VCCINT) 1V 0.95V 0.85V 0.72V
Normalized Facric Performance 1.0x 1.2x 1.6x 1.2x
Normalized Total Power 1.0x 0.7x 0.8x 0.5x
Performance/Watt 1.0x 1.7x 2x 2.4x

7 Series FPGAs & Zynq-7000 SoCs

As the only 28nm FPGAs and SoCs fabricated on a high-performance, low-power process (28HPL), 7 series devices and Zynq-7000 SoCs offer up to 50% total power reduction over previous generation families and superior performance per watt compared to competing 28nm solutions. Architectural and block-level innovations include:

  • Dynamic Function eXchange (DFX) for static power savings
  • Multi-mode I/O control
  • Intelligent clock gating
  • Power binning and voltage scaling

View competitive benchmark summaries as well as detailed benchmark process.

Power Delivery Solutions

Optimized Power Delivery Solutions

Power management requirements are diverse and often unique to a specific use case. As a result, no single power management design can provide the optimal solution. AMD partners with industry-leading power management companies (listed below) to provide a variety of reference designs that map to common use cases, as well as overall guidance on the power supply requirements of AMD Xilinx products.

Hardware Verified Power Solutions

Hardware verified power reference designs are designed to meet all AMD Xilinx power specifications for a targeted device or device family. Hardware verified reference designs ensure that a power solution has been specifically built and tested to meet AMD Xilinx voltage, current, and sequencing specifications. Performance data and design files are made available by the power vendor to boost your design process.

Non-Hardware Verified Solutions

Non-hardware verified solutions are designed to meet all AMD Xilinx power specifications and will meet the requirements of a targeted device or device family. Though not hardware verified, they are guaranteed by datasheet specifications.

Hardware Verified Reference Designs
Vendor Reference Design ACAP Series Power Rail Groupings
Infineon EV-121-D AI Core, Prime Minimum Rails
Intersil-Renesas VERSALDEMOZ1 AI Core, Prime Minimum Rails
Analog Devices, Inc Versal Power Reference Design AI Core, Prime Minimum Rails
Maxim Integrated MAXREFDES1238   AI Core, Prime Minimum Rails
Monolithic Power Systems Efficiency Optimized EVREF105A AI Core, Prime Minimum Rails
Size Optimized EVXLVA_02-A AI Core, Prime Minimum Rails
Texas Instruments
PMP22165 AI Core, Prime Minimum Rails
Non-Hardware Verified Reference Designs
Vendor Reference Design ACAP Series Power Rail Groupings
MPS Size And Efficiency Optimized Designs Premium Minimum Rails, Full Power Management
Size And Efficiency Optimized Designs AI Edge Minimum Rails, Full Power Management
Maxim Integrated Multiphase, PoL Design with PS Overdrive Premium Minimum Rails
Analog Devices, Inc Highly Integrated & Optimized Power Delivery Solution Premium Full Power Management
Hardware Verified Reference Designs
Vendor Reference Design Device Family Target Device(s)
Infineon Xilinx ZCU111 Eval Board RFSoC Gen 1 ZU21 -ZU29
Monolithic Power Systems EVREF0102A - RFSoC Analog Power Module Board
RFSoC Gen 1 ZU21 - ZU29
Intersil-Renesas  ISL8024DEMO2Z - RFSoC Analog Power Module Board RFSoC Gen 1 ZU21 - ZU29
Non-Hardware Verified Reference Designs
Vendor Reference Design Device Family
Target Device(s)
Monolithic Power Systems
Size Optimized Solution using Power Modules
RFSoC Gen 1 ZU21 - ZU29
Highly Integrated Solution with Internal Sequencing RFSoC Gen 1 ZU21 - ZU29
Size Optimized Modular Power Solution RFSoC Gen 2, RFSoC Gen 3 ZU39 - ZU49
Efficiency Optimized Discrete Power Solution RFSoC Gen 2, RFSoC Gen 3 ZU39 - ZU49
Modular Power Solution with PMBus RFSoC Gen 2, RFSoC Gen 3 ZU39 - ZU49
Hardware Verified Reference Designs

Note 1: For more information on Zynq UltraScale+ device use-cases, please see the Power Supply Consolidation Solutions for Zynq UltraScale+ MPSoCs section of  UG583.

Non-Hardware Verified Reference Designs
Vendor Reference Design Target Device(s) Power Rail Groupings
Monolithic Power Systems Cost & Size Optimized Power Delivery ZU1 - ZU3 Minimum Rails & Full Power Management
Hardware Verified Reference Designs
Vendor Reference Design Product Family Target Device(s)
Intersil/Renesas Xilinx VCU128 Eval Board Virtex UltraScale+ VU37P/VU19P1
Monolithic Power Systems Area optimised module based solution for Kintex UltraScale+ Kintex UltraScale+ All KU+
High Power Density Discrete Solution Virtex UltraScale+ VU19P-VU57P
Fully Integrated Solution Using Modules Virtex UltraScale+ VU19P-VU57P
ABB Scalable module based solution for Virtex UltraScale+ Virtex UltraScale+ VU37P
Cyntec

Scalable module based solution for Virtex UltraScale+

Virtex UltraScale+

VU37P

Andapt Programmable PMICs for Minimum Rails Solutions Kintex UltraScale+ KU3P-KU15P
Programmable PMICs for Minimum Rails Solutions Virtex UltraScale+ VU3P, VU5P, VU7P
Programmable PMICs for Full Power Management Virtex UltraScale+ VU31P, VU33P, VU35P
Non-Hardware Verified Reference Designs
Vendor Reference Design Product Family Target Device(s)
Monolithic Power Systems Efficiency Optimised Power Delivery Solution Virtex UltraScale+ VU3P-VU13P, VU31P-VU37P
Size Optimised Power Delivery Solution Virtex UltraScale+ VU3P-VU13P, VU31P-VU37P
Size or Efficiency Optimised Power Delivery Solution Virtex UltraScale+ VU19P, VU27P/29P, VU47P/49P, VU57P
Integrated Sequencing Power Delivery Solution Kintex UltraScale+ KU3P-KU15P
Size Optimised Power Delivery Solution Kintex UltraScale+ KU3P-KU15P
Hardware Verified Reference Designs
Non-Hardware Verified Reference Designs
Vendor Reference Design Product Family Target Device(s)
Monolithic Power Systems Size Optimized Power Module Solution with Scalable VCCINT Kintex UltraScale KU025-KU115
Hardware Verified Reference Designs
Vendor Reference Design Product Family Target Device(s)
TDK Area Optimized Power Module Solution Artix UltraScale+ All AU+
Andapt Programmable Power Delivery Solution for Artix US+ Full Power Management Rails Grouping Artix UltraScale+ All AU+
Non-Hardware Verified Reference Designs
Vendor Reference Design Product Family Target Device(s)
Monolithic Power Systems Cost and Size Optimized Power Delivery  Artix UltraScale+ All AU+
Analog Devices, Inc Low Cost, Minimum Rails Solution Artix UltraScale+ All AU+

Note: All solutions are the responsibility of the specific power vendor. Please check with the appropriate power vendor for additional information and availability.

Upload your Xilinx Power Estimations (XPE) for recommended solutions

Webinars and App Notes

Power Delivery Tools

AMD power delivery partners provide intuitive tools to accelerate power designs, time to market, and PDN simulations to ensure a reliable and optimal performance of power delivery. You can upload AMD Xilinx power files into select vendor tools for a seamless power estimation flow to define your power delivery solution.

Vendor Description Features
Flex Power Modules Flex Power Designer Tool Power Delivery Design and Simulation
Import XPE files
ProGrAnalog LoadSlammer PDN Verification Tool Evaluation/Verification of Power Delivery Network in Hardware
Renesas PowerCompass Multi-Load Configurator & iSim CAD, Power Delivery Design and Simulation Import XPE, XML & PWR files

Note: All tools are the responsibility of the specific power vendor. Please check with the appropriate power vendor for additional information and instructions on how to use.

Power Management Companies

Distribution Partner

Thermal

Thermal Design:

Understating the thermal design limits of an application varies greatly between application types and end markets, a lower power design at a high ambient can experience the same thermal challenges as a high power design at a much lower ambient and so understanding what the limits of a system are is critical for both a successful product and a cost effective product, as overdesign a thermal solution incurs extra cost and complexity to a design.

To this end Xilinx provides DELPHI thermal models for all of current devices, these support both Siemens Flotherm and Ansys IcePak.

*Versal ACAP Models (Coming Soon)

Xilinx U280 airflow & heatmap simulation
Xilinx U280 airflow & heatmap simulation
Xilinx U50 heatmap simulation
Xilinx U50 heatmap simulation

Thermal simulation is a critical step in board design and as indicated in the board methodology process chart, the results of the initial estimation should be used for the thermal solution validation.

board-methodology-process-chart

Thermal Design Partners

Not all customers have access to either the thermal simulation tools or the resources to run a thermal simulation, through the Xilinx Alliance program you can access partners that have Thermal design capability.

Package selection

An important part of device selection is selecting the right package for a successful thermal design. Xilinx devices are available is many package types to cater for different customers requirements, however from a thermal standpoint the Lidless packaging offers the best thermal performance, Xilinx devices are offered in the following packages:


Bare Die – Package Designator (SB/VB)

  • "B" indicates Bare Die, S for 0.8mm & V for 0.92mm package pitch

Lidded -  (SF/VF)

  • "F" For Forged Lid, S for 0.8mm & V for 0.92mm package pitch

Lidless Package (VS/LS)

  • "S" indicated the Stiffener Ring, V for 0.92mm & L for 1mm pitch
  • Provides optimal Thermal Performance


Lidless Overhang Package (VI)

  • "I" indicates a stiffener ring with package overhead (package substrate larger than the BGA footprint)
  • "V" indicates 0.92mm package pitch
  • Provides optimal Thermal Performance
Documentation

Documentation

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Tools

Power Estimation

AMD provides best-in-class tools to estimate pre-implementation power consumption, optimize for lowest power at every design stage, and provide extensive analysis for user-guided optimization. Below are a variety of power-related and AMD industry-leading hardware and software-based tools for designers to get started today.

Training & Support
Video

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