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Overview

Introducing Power Design Manager

Power estimation is critical for many decisions during the FPGA design process—from device selection to system-level power budgeting and thermal design. For many years, Xilinx Power Estimator (XPE) has been a leading FPGA power estimation tool; however, as FPGA, MPSoC, and adaptive compute acceleration platform (ACAP) device sizes and complexities have increased over the last few years, it has become clear that we must have a corresponding upgrade in our power estimation capabilities to better support large, complex device architectures with a range of complex, hard IP blocks.

Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities to even the largest Versal® and Kria™ SOM products. Power Design Manager is the preferred power estimation tool for the Versal product family.

Power Design Manager Features

  • Improved speed and stability for Versal devices
  • Support for Versal AI Core series, Prime series, Premium series, and AI Edge series
  • Support for the Kria K26 SOM and Kria KV260 Starter Kit
  • New XDC wizard user-defined constraints for Vivado® ML Edition power designs and thermal budgets
  • Now available for Windows and Linux
  • Enhanced wizard for Versal ACAP hard IP blocks:
    • DDR Memory Controller (DDRMC)
    • 600G Channelized Multirate Ethernet Subsystem (DCMAC)
    • Multirate Ethernet MAC (MRMAC)
    • 600G Interlaken with FEC (ILKN)
    • 400G High-Speed Crypto (HSC) Engine
    • PCI Express® Integrated Block with DMA/Bridge and Cache Coherent Interconnect (CPM) with PCI Express Base Revision 5.0 (CPM5)

Migration

Easy Migration from XPE to PDM

PDM is recommended for evaluating the power consumption of Versal devices, and offers seamless migration of Versal devices from XPE to PDM. Simply select the Import XPE File option when creating a project in PDM. Once the .xpe file is imported, the PDM tool updates the Versal device resource usage based on the implemented design.

XPE will continue to support all devices prior to the Versal ACAP product family.

Alveo U50 Image

Supported Products

Power Design Manager for Versal devices

Versal Devices Support: Versal AI Core, AI Edge, Prime and Premium Series

Versal AI Core Series Chip Image

AI Core Series

Delivers breakthrough AI inference and wireless acceleration with AI Engines that deliver over 100X greater compute performance than today’s server-class CPUs.

View AI Core Series >

Versal AI Edge Series Chip Image

AI Edge Series

Delivers over 4X AI performance/watt vs. leading GPUs for power- and thermally-constrained edge applications, accelerating the whole application from sensor to AI to real-time control.

View Edge Series >

Versal Prime Series Chip Image

Prime Series

The foundational Versal® ACAP series, providing a wide range of devices with broad applicability across multiple markets.

View Prime Series >

Versal Premium Series Chip Image

Premium Series

Breakthrough integration of networked, power-optimized cores on an adaptable platform for the most challenging compute and networking applications.

View Premium Series >


Kria SOM Support: KV260 vision AI starter kit and K26 SOM

KV260 Vision Starter Kit image

KV260 vision AI starter kit

The development platform for Kria K26 SOMs, the KV260 is built for advanced vision application development without requiring complex hardware design knowledge.

View KV260 >

Kria K26 SOM image

K26 SOM

The newest path to whole application acceleration, the K26 SOM is optimized for edge vision applications requiring flexibility to adapt to changing requirements.

View K26 >

Getting Started

Download PDM and access other resources

Useful Information

Power Design Manager (PDM) is a standalone download for power estimation of these products:

Versal® ACAP: AI Core | Prime | Premium | AI Edge
Kria™ SOM: K26 | KV260

Easily migrate existing power estimates from XPE to PDM to take advantage of the enhanced wizards for Versal devices as well as the expanded OS support.

Sequence & Decoupling

Ensuring that the power delivery is correctly sequenced, decoupled, and consolidated is critical to a smooth board bring up. Via the Power Design page, PDM allows users to consolidate between two support power rails.

 Minimum Rails:

Allows the fewest number of regulators for the selected device; however, this means the application cannot take advantage of any static power savings due to the power management of the domains. Dynamic power savings are still possible via techniques such as clock gating and frequency scaling.

Full Power Management:

Allows full control of the power rails so that maximum power savings are possible—both dynamic savings (from utilizing dynamic power savings such as clock gating or frequency scaling) and static savings (by turning on and off power domains as needed).

PDM will show the supported consolidation and sequencing for these options based on the device selected for core voltage (Low – 0.7v, Mid – 0.8v, and High – 0.88V) with and without PS (processing subsystem) overdrive.

From the power supply table, the power rail groups, DC tolerance, AC ripple, and all current requirements, as well as dynamic decoupling, are also displayed for the user's power estimation.

This ensures that the power delivery is correctly designed for the user’s planned application.

Decoupling capacitors and placement are also shown with PDM. Here are the recommended capacitors for XC (Commercial grade) and XQ (Defense grade) devices.

XC (Commercial grade) recommended capacitors:

Nominal Value Case Size Temp ESR ESL Manf Manf Part Number Ideal Placement to FPGA/MPSoC1
330uF 1210 X6S 1mΩ 4nH Murata GRM32EC80E337ME05L Within 1-1.5" of BGA edge
100uF 0805 X6S 1.5mΩ 2.5nH Murata GRM21BC80G107ME15L Within 1-1.5" of BGA edge
47uF 0603 X6S 2mΩ 2nH Murata GRM188C80E476ME05D Within 1" of BGA edge
22uF 0603 X6S 3mΩ 2nH Murata GRM188C80G226ME15  Within 1" of BGA edge
10uF 0402 X6S 5mΩ 1.5nH Murata GRM155C80E106ME44  Within 1" of BGA edge
1.0uF 0201 X6S 10mΩ 1nH Murata GRM033C80J105ME05   Under BGA between power/GND vias
  1. Ideal placement is to minimize spreading inductance from capacitor to FPGA/MPSoC/ACAP
  2. The decoupling listed above is based on the current PDM design and assumes all of the capacitor placement rules in UG863 have been followed.
  3. We recommend that a full PDN (power decoupling network) simulation is run to validate.
  4. Recommended capacitors for -55C to +105C:

XQ (Defense grade) recommended capacitors:

Nominal Value Case Size Temp/ Change % Manf Manf Part Number Ideal Placement to FPGA/MPSoC1
330µF 7343 TantPoly Kemet T541X337M010AH6510 1-4"
47µF 7343 TantPoly Kemet T541X476M035AH6510 0.5-3"
22µF 1210 X7R Kemet C1210C226K8RAL7800 0.5-2"
2.2µF 0805 X7R Kemet C0805C225K4RAL7800 0-1"
0.47µF 0603 X7R Kemet C0603C474K4RAL7867 0-1"
0.1µF 0402 X7R Kemet C0402C104K4RAL7867 0-1"
  1. Ideal placement is to minimize spreading inductance from capacitor to FPGA/MPSoC/ACAP
  2. The decoupling listed above is based on the current PDM design and assumes all of the capacitor placement rules in UG863 have been followed.
  3. We recommend that a full PDN simulation is run to validate.
  4. Recommended capacitors for -55C to +125C


For more details on validated power reference designs, go to the power delivery solutions page.