Introducing Power Design Manager
Power estimation is critical for many decisions during the FPGA design process—from device selection to system-level power budgeting and thermal design. For many years, Xilinx Power Estimator (XPE) has been a leading FPGA power estimation tool; however, as FPGA, MPSoC, and adaptive compute acceleration platform (ACAP) device sizes and complexities have increased over the last few years, it has become clear that we must have a corresponding upgrade in our power estimation capabilities to better support large, complex device architectures with a range of complex, hard IP blocks.
Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities to even the largest Versal® and Kria™ SOM products. Power Design Manager is the preferred power estimation tool for the Versal product family.
Easy Migration from XPE to PDM
PDM is recommended for evaluating the power consumption of Versal devices, and offers seamless migration of Versal devices from XPE to PDM. Simply select the Import XPE File option when creating a project in PDM. Once the .xpe file is imported, the PDM tool updates the Versal device resource usage based on the implemented design.
XPE will continue to support all devices prior to the Versal ACAP product family.
Power Design Manager for Versal devices
Download PDM and access other resources
Power Design Manager (PDM) is a standalone download for power estimation of these products:
Versal® ACAP: AI Core | Prime | Premium | AI Edge
Kria™ SOM: K26 | KV260
Easily migrate existing power estimates from XPE to PDM to take advantage of the enhanced wizards for Versal devices as well as the expanded OS support.
Ensuring that the power delivery is correctly sequenced, decoupled, and consolidated is critical to a smooth board bring up. Via the Power Design page, PDM allows users to consolidate between two support power rails.
Allows the fewest number of regulators for the selected device; however, this means the application cannot take advantage of any static power savings due to the power management of the domains. Dynamic power savings are still possible via techniques such as clock gating and frequency scaling.
Full Power Management:
Allows full control of the power rails so that maximum power savings are possible—both dynamic savings (from utilizing dynamic power savings such as clock gating or frequency scaling) and static savings (by turning on and off power domains as needed).
PDM will show the supported consolidation and sequencing for these options based on the device selected for core voltage (Low – 0.7v, Mid – 0.8v, and High – 0.88V) with and without PS (processing subsystem) overdrive.
This ensures that the power delivery is correctly designed for the user’s planned application.
Decoupling capacitors and placement are also shown with PDM. Here are the recommended capacitors for XC (Commercial grade) and XQ (Defense grade) devices.
|Nominal Value||Case Size||Temp||ESR||ESL||Manf||Manf Part Number||Ideal Placement to FPGA/MPSoC1|
|330uF||1210||X6S||1mΩ||4nH||Murata||GRM32EC80E337ME05L||Within 1-1.5" of BGA edge|
|100uF||0805||X6S||1.5mΩ||2.5nH||Murata||GRM21BC80G107ME15L||Within 1-1.5" of BGA edge|
|47uF||0603||X6S||2mΩ||2nH||Murata||GRM188C80E476ME05D||Within 1" of BGA edge|
|22uF||0603||X6S||3mΩ||2nH||Murata||GRM188C80G226ME15||Within 1" of BGA edge|
|10uF||0402||X6S||5mΩ||1.5nH||Murata||GRM155C80E106ME44||Within 1" of BGA edge|
|1.0uF||0201||X6S||10mΩ||1nH||Murata||GRM033C80J105ME05||Under BGA between power/GND vias|
|Nominal Value||Case Size||Temp/ Change %||Manf||Manf Part Number||Ideal Placement to FPGA/MPSoC1|
For more details on validated power reference designs, go to the power delivery solutions page.