Vivado Design Suite - HLx Editions
Productivity. Multiplied.
Vivado Design Suite HLx Editions - Accelerating High Level Design
Vivado® Design Suite HLx Editions include Partial Reconfiguration at no additional cost with the Vivado HL Design Edition and HL System Edition. In-warranty users can regenerate their licenses to gain access to this feature. Partial Reconfiguration is available for Vivado WebPACK™ edition at a reduced price.
The new HLx editions supply design teams with the tools and methodology needed to leverage C-based design and optimized reuse, IP sub-system reuse, integration automation and accelerated design closure. When coupled with the UltraFast™ High-Level Productivity Design Methodology Guide, this unique combination is proven to accelerate productivity by enabling designers to work at a high level of abstraction while facilitating design reuse.
- Software-defined IP Generation with Vivado High-Level Synthesis
- Block-based IP Integration with Vivado IP Integrator
- Model-based Design Integration with Model Composer and System Generator for DSP
- Vivado Logic Simulation
- Integrated Mixed Language Simulator
- Integrated & Standalone Programming and Debug Environments
- Accelerate Verification by >100X with C, C++ or SystemC with Vivado HLS
- Verification IP
- 4X Faster Implementation
- 20% Better Design Density
- Up to 3-Speedgrade Performance Advantage for the low-end & mid-range and 35% Power Advantage in the high-end
Now available in the Vivado® Design Suite HLx Editions 2018.1 Release
Download Vivado Design Suite 2018.1 now, with support for:
- Zynq UltraScale+™ RFSoC and Virtex UltraScale+ HBM devices
- Increased productivity via ease of use improvements in IP flows and IP Integrator
- New helper IPs and device support for Partial Reconfiguration
- New capabilities and functions in Model Composer
- Improved UltraScale+ Implementation: 5.5% higher Fmax, 1.6x faster compile times
- Production devices introduced in this release
- Zynq UltraScale+ MPSoC: XCZU11EG (-3), XCZU15EG (-3), XCZU17EG (-3), XCZU19EG (-3)
- Kintex® UltraScale+: XCKU3P (-3), XCKU5P (-3), XCKU11P (-3), XCKU13P (-3), XCKU15P (-3)
- Virtex UltraScale+: XCVU3P (-3), XCVU5P (-3), XCVU7P (-3), XCVU9P (-3)
- Artix®-7 and Spartan®-7: XC7A25T (-2LE(0.9V)), XC7A12T (-2LE(0.9V)), XC7S100 (-1,-2), XC7S75 (-1,-2), XC7S25 (-1Q), XA7S25 (-1I,-2I,-1Q), XA7A25T (-1I, -2I, -1Q), XA7A12T (-1I,-2I,-1Q)
- New Spartan-7 devices enabled: XC7S6, XC7S15, XA7S6 and XA7S15
- New devices enabled in WebPACK
- Artix-7: XC7A12T, XC7A25T
- XA Artix-7: XA7A12T, XA7A25T
- XA Spartan-7: XA7S25
Read about all of this and more in the Vivado 2018.1 release notes.
For latest trends to accelerate your productivity, check out the Vivado Expert Blog
The Vivado® Design Suite offers a new approach for ultra-high productivity with next generation C/C++ and IP-based design. When coupled with the new UltraFast™ High-Level Productivity Design Methodology Guide, users can realize a 10-15X productivity gain over traditional approaches. The Vivado HLx Editions are:
- Vivado HL Design Edition: Includes Partial Reconfiguration and Vivado High-Level Synthesis
- Vivado HL System Edition: All features of the Design Edition plus System Generator for DSP
- Vivado HL WebPACK™ Edition: no-cost, device-limited version of the Vivado HL Design Edition
- Vivado Lab Edition: Smaller footprint, easy to install in lab environments, including all programming and debug capabilities in the full Design Edition
Download a 30-day Evaluation and get started today!
Vivado Design Suite - HLx Editions
| Vivado Design Suite - HLx Edition Features | Vivado HL Design Edition | Vivado HL System Edition | Vivado Lab Edition | Vivado HL WebPACK Edition (Device Limited) | Free 30-day Evaluation |
|---|---|---|---|---|---|
| Accelerating Implementation | |||||
| Synthesis and Place and Route |  |
|
|
|
|
| Partial Reconfiguration | |
|
* | |
|
| Accelerating Verification | |||||
| Vivado Simulator | |
|
|
|
|
| Vivado Device Programmer | |
|
|
|
|
| Vivado Logic Analyzer | |
|
|
|
|
| Vivado Serial I/O Analyzer | |
|
|
|
|
| Debug IP (ILA/VIO/IBERT) | |
|
|
|
|
| Accelerating High Level Design | |||||
| Vivado High-Level Synthesis | |
|
|
|
|
| Vivado IP Integrator | |
|
|
|
|
| System Generator for DSP | * | |
* | |
|
| Model Composer | * | * | * | ||
* Can be purchased as an option.
HL Design Edition
Buy Online From Xilinx
Software Only
-
Buy Node-Locked License
- Price: $2995
- Lead Time: Immediate
-
Buy Floating License
- Price: $3595
- Lead Time: Immediate
HL System Edition
Buy Online From Xilinx
Software Only
-
Buy Node-Locked License
- Price: $3495
- Lead Time: Immediate
-
Buy Floating License
- Price: $4295
- Lead Time: Immediate
Training Courses
Xilinx hands-on FPGA and Embedded Design training provides you the foundational knowledge necessary to begin designing right away. These programs target both engineers new to FPGA technology and experienced engineers developing complex connectivity, digital signal processing, or embedded solutions. Contact your local Sales Rep or Authorized Training Provider to see if your company has any Training Credits available. Learn more
Vivado QuickTake Video Tutorials
Xilinx is developing QuickTake Video Tutorials in order to assist our users in making the transition from the ISE software tools to the Vivado® Design Suite. This entire solution is brand new, so we can't rely on previous knowledge of the technology. Xilinx recognizes that not everyone has the time to read through the User Guide or perform software interactive tutorials. Learn more
Vivado HLx Editions QuickTake Video Tutorials
Vivado QuickTake videos take a deep dive into the Vivado® HLx Editions giving you individualized videos on topics ranging from installation and licensing, to design flow overview, high-level synthesis and beyond. Created by the Vivado development and expert team, Vivado QuickTake tutorials provide on-demand content and helpful tips & tricks – all at your fingertips.
Getting Started
Jump start your installation and design with the following videos.
Design Flows
Learn more about Vivado by selecting the following design flows.
