Enabling faster design iterations and quickly meeting your FMAX targets
Vivado is the design software for AMD adaptive SoCs and FPGAs. It includes: Design Entry, Synthesis, Place and Route, Verification/Simulation tools.
Learn how advanced features in Vivado design software helps hardware designers reduce compile times and design iterations, while more accurately estimating power for AMD adaptive SoCs and FPGAs. (Infographic - May 2023)
Watch this video for a quick overview about Vivado.
Meeting Fmax targets
Ease of use enhancements in IPI, DFX, Debug and Simulation
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Achieving your FMAX target in a high-speed design is one of the most challenging phases of the hardware design cycle. Vivado brings unique features such as Report QoR Assessment (RQA), Report QoR Suggestions (RQS) and Intelligent Design Runs (IDR) –these features help you close timing. Using RQA, RQS and IDR will help converge on your performance goals in days instead of weeks resulting in huge productivity gains.
Design iterations are common as devlopers add new features and debug their design. In many cases these iterations are incremental changes and in most cases the changes are within a small portion of the design. The Vivado ML Edition offers two key technologies that significantly reduce design iteration times: Incremental compile and Abstract Shell.
While designing Adaptive SoCs and FPGA, early and accurate power estimation is critical to driving crucial design decisions. Power Design Manager is a next generation power estimation tool engineered to provide accurate power estimation early in the design process for large and complex devices such as Versal and UltraScale+ families. This tool was specifically designed to provide accurate power estimations for devices with multiple complex hard IP blocks.
Vivado Design Flow
Vivado supports design entry in traditional HDL like VHDL and Verilog. It also supports a graphical user interface-based tool called the IP Integrator (IPI) that allows for a Plug-and-Play IP Integration Design Environment.
The Vivado ML Edition delivers the best-in-class synthesis and implementation for today’s complex FPGAs and SOCs with built-in capabilities for timing closure and methodology.
The UltraFast methodology report (report_methodology) that is available in the default flow of Vivado, helps users constrain their design, analyze results, and close timing.
Verification and HW Debug is critical to ensure the functionality, performance, and reliability of the final FPGA implementation. Vivado’s verification features enable efficient validation of design functionality while its comprehensive debugging features empower engineers to efficiently locate and resolve issues within complex FPGA designs.
Dynamic Function eXchange (DFX) allows designers to dynamically modify sections of the FPGA designs on-the-fly. Designers can download partial bitstreams to the FPGA while the remaining logic continues to operate. This opens a world of possibilities for real time design changes and performance enhancements. Dynamic Function eXchange can allow designers to move to fewer or smaller devices, reduce power, and upgrade systems in real-time.
Vivado ML Standard Edition is a no-cost, device-limited version of Vivado ML.
Vivado ML Enterprise Edition includes support for all AMD devices.
Self-Service Resources for Vivado