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Accelerating Verification

Vivado Rapid Verification Solution

High-quality and rapid verification closure is ever more important with increasing complexities of programmable devices. Meeting the verification challenges of today’s complex devices requires multitudes of tools and technologies at various levels of design. Vivado® Design Suite delivers these tools and technologies in a cohesive environment for accelerated verification of block and chip level designs.

The core verification engines of Vivado Design Suite are mixed-language simulator and hardware debug tool. These high-performance & high-capacity verification tools allows designers to identify bugs in less time. To further reduce debugging time and efforts, Vivado Design Suite provides Verification IPs of standard interface protocols. And last but not least, Vivado® Design suite automates simulation flow by integrating third-party simulators to further augment verification requirements needed by cutting-edge designs.

rapid-verification-solution

Verification IPs

While usage of industry standard interface in SoC design is ubiquitous, modeling of standard interface protocols still remains a very time consuming and challenging task. Verification IPs (VIP) are reusable components that accelerate the verification of standard interfaces. Flexible architecture of these VIPs makes them easy to fit in any verification environment. These VIPs supports all major simulators and are available at no cost to Xilinx customers.

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Vivado Simulator

Powerful Vivado Simulator is an integral part of Vivado Design Suite. This mixed-language simulator supports both functional and timing simulation and offers superior debugging capabilities. The simulator boasts features such as incremental compilation and pre-compiled IPs to cut compilation time significantly. Vivado Simulator makes it easy to debug the design using breakpoints and cross-probing features and its advanced waveform viewer can load large amounts of data very quickly.

Learn more about Vivado Simulator.

Simulation Flow

Vivado Design Suite supports all major HDL simulators for enterprise verification usage. The simulation flow allows both interactive and script-driven simulation and is integrated to support all Vivado environments such as IP, RTL and IP Integrator. The simulation flow is built on top of the Xilinx Tcl Store thus enabling the capability for additional 3rd party tools to be integrated with Vivado.

Learn more about Vivado Simulation Flow.

Vivado Hardware Debug & Programming

Hardware debug and programming capabilities in Vivado arm the user with the right tool set to tackle today’s complex designs. These capabilities provide the desired visibility into design operation and its interaction with the rest of the system. By being effective at resolving issues quickly, users increase their productivity and accelerate the debugging phase of their design.

Various IPs, flows, and tools come together to provide a coherent debug environment that allows for probing specific parts of the design at different stages of the design cycle. From low-level debug of internal nets, transceiver hard blocks, or memory interfaces to interface-level debug of IP blocks, incremental debug flows, and remote debug of designs over PCIe or Ethernet, various advanced methodologies and techniques within the tool deliver more debug turns per day and meet users exact needs.

Learn more about Vivado Hardware Debug.

Virtual Emulation

Xilinx’s open source virtual emulation platform QEMU is a powerful tool for system development. It allows you to model early and integrate continuously without using any cables and boards. Behavioral correctness of any system can be validated early using QEMU since it allows putting all system pieces together such as the software stack, SoC & peripherals, programmable IPs and board devices.

Learn more about Virtual Emulation.