Based on an ASIC-class architecture, AMD FPGAs combine multi-hundred giga-bit-per-second I/O bandwidth with over 20 TeraMACs of fixed point DSP performance in the Virtex™ UltraScale+™ family. The AMD DSP slice and its parallelism is key to the achievable DSP performance in the latest generation of AMD FPGAs.

DSP Slice Architecture

The UltraScale™ DSP48E2 slice is the 5^th generation of DSP slices in AMD architectures.

This dedicated DSP processing block is implemented in full custom silicon that delivers industry leading power/performance allowing efficient implementations of popular DSP functions, such as a multiply-accumulator (MACC), multiply-adder (MADD) or complex multiply.

The slice also provides capabilities to perform different kinds of logic operations, such as AND, OR and XOR operations (UG579).

UltraScale architecture builds on the success of 7 series (DSP48E1), with further enhancements:

• Wider multiplier (27 x 18 bits)
• Ability to square the output of the Pre-Adder via the Squaring MUX
• New wide MUX feature allowing for a true 3 input adder after the multiplier

These enhancements help DSP critical applications perform more computation within the DSP48E2 slice before going into the FPGA fabric, ultimately leading to both resource and power savings.

DSP48E1 (7 Series) vs DSP48E2 (UltraScale) Slice Features

Featured Videos:

1. Utilizing the Squaring MUX in the DSP48E2 slice
2. Utilizing the Wide MUX Feedback in the DSP48E2 slice

Tools and Flows

Depending on your designing preferences, AMD has tools supporting RTL, C/C++ and model-based design entry. This flexibility in the design flow, along with an extensive DSP IP catalog, facilitates easier adoption of AMD tools and devices.

The Vivado IDE works as a design cockpit for system level design which provides the ability to build your complete design, implement it and write out a bit-file to program your device.

Visit Tools, Libraries & Frameworks for more information.

DSP Performance Metrics

The following table shows some of the key DSP performance metrics for 7 Series, UltraScale and UltraScale+ families. For SoC device performance, see Software Developer section.

Notes:

1. Logic Cells used for 7-Series only
2. Using the pre-adder DSP performance can be increased 2x for symmetric filters
3. Please refer to WP486 – Deep Learning with INT8 Optimization on AMD Devices
4. Single Precision Floating Point performance using Floating Point Operator core with 3 DSP slices
5. Single Precision Floating Point performance using Floating Point Operator core with 4 DSP slices
6. Half Precision Floating Point performance using Floating Point Operator core with 2 DSP slices

Useful Design Techniques and Information

To achieve the most optimal and efficient usage of the DSP48 slices within AMD FPGAs, the following information and techniques should be reviewed and utilized where possible.

• Utilize the DSP slice user guides as a cumulative resource (AR68594)
• AMD LogiCORE DSP48 Macro provides an easy-to-use interface to configure the DSP48 slice
• Time Division Multiplexing the DSP Slice to improve efficiency and throughput (AR68595)
• Working with Floating Point, AMD provides the Floating-Point Operator IP core, which includes the ability to convert between data-types, e.g. Floating Point to Fixed Point

AMD has introduced software development environments and a comprehensive set of familiar and powerful tools, libraries and methodologies which allow software developers to target AMD FPGAs and SoCs with ease. With these high level abstraction environments like Vivado High Level Synthesis (HLS), SDAccel and SDSoC, AMD can offer GPU-like and familiar embedded application development and runtime experiences for C, C++ and/or OpenCL development.

AMD SoCs and MPSoCs

The Zynq UltraScale+ MPSoC and the Zynq 7000 families combine a powerful processing system (PS), incorporating ARM® Cortex® processors, and user-programmable logic (PL), in a single device.

Application Profiling for Acceleration

SDSoC provides the ability to profile a given application and allows for the creation of hardware accelerators to run more efficiently in the Programmable Logic (PL), where the flexibility and parallelism of the FPGA are leveraged to provide large performance improvements. This also enables other functions of the application to run in the Processing System (PS) in parallel if desired.

By targeting AMD FPGAs and SoCs, many DSP and embedded applications will see improvements in efficiency and reduced power for their applications.

Features and DSP Performance of AMD SoC Devices

The following tables shows some of the key features and DSP performance metrics for both AMD Zynq 7000 SoC and Zynq UltraScale+ MPSoC families. For non-SoC device performance, visit the Hardware Designer section.

Notes:

1. All performance calculations based of -2 speed grade parts for Zynq 7000 SoC and -3 for Zynq UltraScale+ MPSoC
2. Using the pre-adder DSP performance can be increased 2x for symmetric filters
3. Please refer to WP486 – Deep Learning with INT8 Optimization on AMD Devices (Not applicable for Zynq devices)
4. Single Precision Floating Point performance using Floating Point Operator core with 3 DSP slices
5. Single Precision Floating Point performance using Floating Point Operator core with 4 DSP slices
6.  Half Precision Floating Point performance using Floating Point Operator core with 2 DSP slices

To learn more about AMD SoCs and MPSoCs, go to:

• AMD SoCs & MPSoCs
• AMD Software Zone

DSP in the Processing Subsystem

The Processing System (PS) provides DSP processing capabilities by way of the different ARM processing cores.

For more information on DSP capabilities in the ARM processors, visit:

• Cortex-A Series Family
• SIMD and Advanced SIMD (NEON) technologies
• ARM Floating Point Architecture

Some useful examples can be found at the following locations:

For Zynq UltraScale+ MPSoC, see UG1211 for a demonstration of an FFT using the ARM NEON instruction set.

For Zynq 7000 SoC, the following Tech Tips are available on Xilinx wiki when targeting the Cortex-A9 and ARM SIMD:

• Building ARM NEON Library Tech Tip 2014.3
• Running ARM Library Tests Tech Tip 2014.3

AMD Data-type Support

AMD has very flexible data-type support in their devices. Varying precisions of Fixed Point, Floating Point and Integer are supported natively in AMD tools with Floating Point being implemented with the aid of the Floating Point Operator IP core.

Floating Point designs implemented on FPGAs will always lead to higher resource and power usage compared to Fixed Point or Integer implementations. Converting to a fixed point solution where possible will bring large benefits:

• Fewer FPGA resources
• Lower power
• Lower cost

For more details on the benefits of converting from floating point to fixed point data types, please read WP491.

Benchmarks

The below tables show a small selection of algorithms and possible performance improvements by using an AMD device and in particular the fabric in the programmable logic (PL) to accelerate the design.

Note 1: ARM: Quad-core A53 run on Raspberry Pi @ 1200MHz
Note 2: Nvidia benchmarks were done using Tegra X1
Note 3: Optical Flow (LK) – Window Size 11x1

Note 1: Cortex-A9 core used only on the Zynq devices when targeting ARM
Note 2: TI benchmarks were done using C66 DSP core

AMD high-level design tools like Vivado System Generator for DSP and Vivado High Level Synthesis provide a level of abstraction that empower system architects and domain experts to rapidly evaluate new algorithms and focus on developing the differentiating parts of their design. The complete AMD DSP solution is a combination of these design tools, IP, reference designs, methodologies and boards that work together to get to a working production design in the shortest time possible.

Vivado System Generator for DSP

The Vivado System Generator for DSP is a Model-Based design tool that leverages the MATLAB and Simulink environment to define, test and implement production quality DSP algorithms in programmable logic in a fraction of traditional RTL development times.

The tool provides:

• 100+ optimized DSP blocks, many with C simulation models for 2-3X faster simulation vs RTL
• Integration of RTL, IP, Simulink, MATLAB and C/C++ components of a DSP system
• Bit and cycle accurate floating and fixed-point simulations
• Hardware co-simulation to accelerate simulation and validate algorithm on working hardware
• Automatic code generation from Simulink to packaged IP or low-level HDL
• Automatic generation of HDL test bench, including test vectors

Learn more about Vivado System Generator for DSP:

• Introduction to System Generator (Video)
• Using Hardware Co-simulation with System Generator for DSP (Video)
• System Generator for DSP User Guide (Documentation)

Vivado High Level Synthesis

Vivado High-Level Synthesis, included as a no cost upgrade in all Vivado HLx Editions, enables portable C, C++ and System C algorithm specifications to be directly targeted into AMD devices without the need to create RTL. Just as there are compilers from C/C++ to different processor architectures, the HLS compiler provides the same functionality from C/C++ to AMD FPGAs.

Learn more about Vivado High Level Synthesis:

• Getting Started with Vivado High-Level Synthesis (Video)
• Video High Level Synthesis User Guide (Documentation)