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Highest Performance &
Integration on FinFET

Product Advantages

Virtex UltraScale+ Product Advantage

Based on the UltraScale architecture, the latest Virtex® UltraScale+ devices provide the highest performance and integration capabilities in a FinFET node, including the highest signal processing bandwidth at 21.2 TeraMACs of DSP compute performance. They also deliver the highest on-chip memory density with up to 500Mb of total on-chip integrated memory, plus up to 8GB of HBM Gen2 integrated in-package for 460GB/s of memory bandwidth. Virtex UltraScale+ devices deliver significant capabilities with integrated IP for PCI Express, Interlaken, 100G Ethernet with FEC, and Cache Coherent Interconnect for Accelerators (CCIX). Xilinx 3D ICs utilize stacked silicon interconnect (SSI) technology to break through the limitations of Moore’s law and deliver the capabilities to satisfy the most demanding design requirements. Third-generation 3D IC technology provides registered inter-die routing lines enabling >600 MHz operation, with abundant and flexible clocking. As the industry’s most capable FPGA family, the devices are ideal for applications ranging from 1+ Tb/s networking, smart NIC, machine learning, and Data Center Interconnect, to fully-integrated radar/early-warning systems.

Value Features
Programmable System Integration
  • Up to 8GB of HBM Gen2 integrated in-package
  • Up to 500Mb of on-chip memory integration
  • Integrated 100G Ethernet MAC with KR4-FEC and 150G Interlaken cores
  • Integrated blocks for PCI Express Gen 3x16
Increased System Performance
  • Over 2X system-level performance per watt over Virtex-7 FPGAs
  • Up to four speed-grade improvement with high utilization
  • Up to 128-33G transceivers deliver 8.4 Tb of serial bandwidth
  • 58G PAM4 transceivers with KP4-FEC enable data transmission at 50G+ line rates
  • 460GB/s HBM bandwidth, and 2,666 Mb/s DDR4 in a mid-speed grade
BOM Cost Reduction
  • A 5:1 card reduction for 1 Tb MuxSAR transponder
  • UltraRAM for on-chip memory integration
  • VCXO and fractional PLL integration reduces clocking component cost
Total Power Reduction
  • Up to 60% lower power vs. 7 series FPGAs
  • Voltage scaling options for performance and power
  • Tighter logic cell packing reduces dynamic power
Accelerated Design Productivity
  • Seamless footprint migration from 20nm planar to 16 nm FinFET+
  • Co-optimized with Vivado Design Suite for rapid design closure
  • SmartConnect technology for intelligent IP integration

All comparisons based upon 28 nm Virtex-7 FPGAs

Product Table

Virtex UltraScale+ Product Table

System Logic Cells (K) 862 1,314 1,724 2,586 2,835 3,780 2,835 3,780 962 962 1,907 2,852
DSP Slices 2,280 3,474 4,560 6,840 9,216 12,288 9,216 12,288 2,880 2,880 5,952 9,024
Memory (Mb) 115.3 168.2 230.6 345.9 341 455 341 455 32,894 65,662 65,788 65,913
GTY/GTM Transceivers (32.75/58 Gb/s) 40/0 80/0 80/0 120/0 96/0 128/0 32/48 32/48 32/0 32/0 64/0 96/0
I/O 520 832 832 832 624 832 520 676 208 208 416 624
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