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PCI Express and Xilinx Technology

High performance, low power Integrated Blocks for PCI Express

Overview

Overview

PCI Express® (PCIe) is a general-purpose serial interconnect suitable for a broad range of applications across Communications, Data center, Enterprise, Embedded, Test & Measurement, Military and other markets. It can be used as peripheral device interconnect, chip-to-chip interface and as a bridge to many other protocol standards.

Xilinx provides high performance, low power Integrated Blocks for PCI Express as a hardened sub-system in many devices.

Xilinx also provides PCIe DMA and PCIe Bridge hard and soft IP blocks that utilize the Integrated Block for PCI Express, boards with PCI Express connectors, connectivity kits, reference designs, drivers and tools to make it easy to implement PCIe based designs.

Please select a Device Family in order to review the Xilinx PCIe solution portfolio for that family.

Versal Solutions

Versal Solutions

Systems leveraging implementations of the PCI Express Specification are pervasive in data center, communications, and embedded applications. The multiple connectivity options available in the Versal® architecture directly support users’ needs to focus on their core competency while leveraging advanced standards-based interfaces. The integrated blocks for PCI Express in the Versal architecture offer premium performance levels, with ease of use and efficiency over fully soft IP solutions. The Versal architecture integrates four types of integrated blocks for PCI Express:

  • CPM5, an integrated block for PCI Express Rev. 5.0 with DMA and CCIX Rev. 1.1
  • PL PCIE5, an integrated block for PCI Express Rev. 5.01
  • CPM4, an integrated block for PCI Express Rev. 4.0 with DMA and CCIX Rev. 1.0
  • PL PCIE4, an integrated block for PCI Express Rev. 4.0

Footnote:
1 Supports CCIX via a combination of integrated block with additional soft IP solution.

CPM5, PL PCIE5, CPM4, and PL PCIE4, in conjunction with available GTYP and GTY transceivers, enable interface operation at specification-defined data rates. These range from 2.5GT/s per lane with one lane (Gen1x 1) up to their rated maximum link configurations, which can reach 32GT/s per lane with 8 lanes (Gen5x 8) and 16GT/s per lane with 16 lanes (Gen4x 16). The table below is a summary of key characteristics of the integrated blocks for PCI Express in the Versal architecture. Please also refer to the Versal Architecture and Product Data Sheet: Overview (DS950), for additional information on available resources and capabilities based on orderable device, package, and speed grade combinations.

  Versal Architecture Integrated Blocks for PCI Express
CPM5 PL PCIE5 CPM4 PL PCIE4
Associated
Specifications
PCIe Rev. 5.0
CCIX Rev. 1.1
PCIe Rev. 5.0
CCIX Rev. 1.1
PCIe Rev. 4.0
CCIX Rev. 1.0
PCIe Rev. 4.0
Max PCIe
Link Configs
2 x Gen5x 8
Gen4x 16
2 x Gen4x 8
Gen5x 4
Gen4x 8
Gen3x 16
Gen4x 16
2 x Gen4x 8
Gen4x 8
Gen3x 16
PCIe Port
Type Support
EP, RP,
Switch
EP, RP,
Switch
EP, RP,
Switch
EP, RP,
Switch
Key PCIe
Features
SR-IOV
16PF / 4KVF
SR-IOV
8PF / 4KVF
SR-IOV
4PF / 252VF
SR-IOV
4PF / 252VF
Optional
Integrated DMAs
2 x QDMA
(4K queues)
- Choice of One:
QDMA (2K queues)
XDMA
-
CCIX Data Rates
and Features
16GT/s, 20GT/s
25GT/s, 32GT/s
Integrated Cache
16GT/s, 20GT/s
25GT/s, 32GT/s
Soft IP Solution
16GT/s, 20GT/s
25GT/s
Integrated Cache
-

CPM5, PL PCIE5, CPM4, and PL PCIE4 can be used at reduced link configurations to optimize product designs for cost, support novel form factors, alleviate board complexity, and shrink power budgets. Additionally, reduced link configurations can support lower programmable logic resource utilization, depending on the nature of any soft IP solutions used to expand the application-level capabilities of these integrated blocks. CPM5, PL PCIE5, CPM4, and PL PCIE4 can be configured as Endpoint (EP), Root Port (RP), and switch port types. See Product Guide PG343 and Product Guide PG346.

Xilinx enables users to focus design investment in their areas of greatest value by delivering pre-verified high-performance DMA and bridge subsystems for the integrated blocks for PCI Express in the Versal architecture. Available DMA and bridge subsystem options include:

  • CPM5, which contains two controllers for PCI Express, also integrates two instances of a QDMA and bridge subsystem from the Xilinx IP portfolio. Use of the integrated DMA is optional, and each instance is independently customizable. The QDMA subsystems provide scalable queue-based DMA for moving enormous volumes of data with low latency, plus support for multiple physical and virtual functions commonly required by enterprise class products. Data can be moved with memory-mapped techniques, including the programmable network on chip (NoC), or with streaming techniques, into the Versal ACAP’s Adaptable Engines. The subsystems also include bridge functionality to AXI interconnect.
  • CPM4, which contains two controllers for PCI Express, also integrates one instance of a QDMA/XDMA and bridge subsystem from the Xilinx IP portfolio. Use of the integrated DMA is optional, and when used, can be configured as a QDMA subsystem like that in the CPM5, or as an XDMA subsystem. Data can be moved with memory-mapped techniques, including the programmable NoC, or with streaming techniques, into the Versal ACAP’s Adaptable Engines. The subsystem also includes bridge functionality to AXI interconnect.
  • PL PCIE5 and PL PCIE4, which are individual controllers for PCI Express, are supported by soft IP implementations of DMA, and bridge subsystems available at no cost through the Vivado® Design Suite’s IP Catalog.

For most users, the available DMA and bridge subsystems are time-saving infrastructure, providing high-performance turnkey data movement. See Product Guide PG344 and Product Guide PG347. For users seeking to attach their own DMA and bridge subsystem—for preserving their driver and application software investment, or to customize or optimize functionality using intimate knowledge of the end application—options are available to bypass DMA in the integrated blocks that contain it. For ultimate freedom to implement fully custom solutions, Xilinx also provides a soft IP core PHY for PCI Express through the Vivado IP Catalog, enabling designers to attach their own controllers for PCI Express to available GTYP and GTY transceivers.

UltraScale+ Solutions

UltraScale+ Solutions

Xilinx 16nm UltraScale+™ devices integrate many essential PCI Express features required for today’s Data center, Communications and embedded applications.  UltraScale+ devices use two types of integrated blocks: PCIE4 and PCIE4C, with most devices using the PCIE4 blocks.

The PCIE4 blocks are compliant to PCI Express Base Specification v3.1 and support up to Gen3 x16, and can also be configured for lower link width and speeds. The PCIE4 block does not support Gen4 operation.

PCIE4C blocks are compliant to the PCI Express Base Specification v3.1 supporting up to 8.0GT/s (Gen3) and compatible with PCI Express Base Specification v4.0 supporting up to 16.0GT/s (Gen4). PCIE4C blocks are also compliant with CCIX Base Specification v1.0 Version 0.9, supporting speeds up to 16.0GT/s.  PCIE4C blocks support up to 16 lanes at Gen3 or up to 8 lanes at Gen4 and can be configured for lower link widths and speeds to conserve resources and power.

Some devices, such as Virtex UltraScale+™ HBM FPGAs and Virtex UltraScale+ 58G FPGAs, have only PCIE4C blocks or a combination of both PCIE4 and PCIE4C blocks. The PCIE4C block can implement both PCI Express and CCIX while PCIE4 blocks can implement only PCI Express.

All integrated blocks for PCIe in the UltraScale architecture can be configured as Endpoint or Root Port.  The Root Port can be used to build the basis for a Root Complex, to allow custom chip-to-chip communication via the PCI Express protocol, and to attach ASSP Endpoint devices, such as Ethernet Controllers or Fibre Channel HBAs or NVMe SSDs, to the FPGA, MPSoC, or RFSoC.

The Integrated Block for PCI Express IP is hardened in silicon, and supports:

  • Operation up to Gen3 x16 in all devices with integrated blocks for PCI Express, plus compatibility with Gen4 x8 in select devices offering PCIE4C blocks.  For specific link widths and rates that are supported, consult the IP product guide for the desired IP (PG213, PG195 or PG302).  For details about PCIE4C block compatibility with Gen4 x8, see PG213.
  • Supports 4 physical functions and 252 virtual functions in support of Single Root I/O Virtualization (SR-IOV) to share I/O resources.
  • Expanded number of tags (256) to support more requests, enabling improvements in overall system performance.
  • Integrated MSI-X tables.

Xilinx also offers high performance DMA and Bridge solutions as soft IP:

  • Xilinx QDMA IP sub-system is our leading DMA solution for PCIe.  The QDMA provides support for SR-IOV with multiple Physical and Virtual Functions with scalable queues. The QDMA also provides AXI Bridge functionality.  See Product Guide PG302 for more details.
  • Xilinx XDMA IP sub-system is our legacy DMA solution for PCIe, widely used by customers. The XDMA also provides AXI Bridge functionality.  See Product Guide PG195 for further details.

For ultimate freedom to implement fully custom solutions, Xilinx also provides a soft IP core PHY for PCI Express, enabling designers to attach their own controllers for PCI Express to available transceivers.

UltraScale Solutions

UltraScale Solutions

Xilinx 20nm UltraScale™ devices integrate many essential PCI Express features required for today’s Data center, Communications and embedded applications.

The Integrated Block for PCI Express IP is hardened in silicon, and supports:

  • Native Gen3 x8* Integrated PCIe block
  • Supports 64 tags for PCIe requests
  • Supports multi-vector MSI for up to 32 vectors and MSI-X
  • See Product Guide PG156 for further details

Xilinx also offers high performance DMA and Bridge solutions as soft IP:

  • Xilinx XDMA IP sub-system is our production PCIe DMA solution, widely used by customers. See Product Guide PG195 for more information.
  • Xilinx provides a production AXI Memory Mapped to PCI Express Bridge IP. See Product Guide PG194 for further details.

*For specific link widths and speeds that are supported, see the appropriate Product Guide for the desired IP (PG156, PG195 or PG194)

7 Series Solutions

7 Series Solutions

Xilinx 28nm 7 Series devices integrate many essential PCI Express features required for today’s Data center, Communications and embedded applications.

The Integrated Block for PCI Express IP is hardened in silicon, and supports:

  • Native Gen3 x8* Integrated PCIe block
  • Supports 64-bit and 128-bit data widths
  • See Product Guide PG054 for further details

Xilinx also offers high performance DMA and Bridge solutions as soft IP:

  • Xilinx XDMA IP sub-system is our production PCIe DMA solution, widely used by customers.  See Product Guide PG195 for more information.
  • Xilinx provides a production AXI Memory Mapped to PCI Express Gen2 IP. See Product Guide PG055 for further details.

*For specific link widths and speeds that are supported, see the appropriate Product Guide for the desired IP (PG054, PG055 or PG195)

Documentation

Documentation

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