Xilinx Artix-7 FPGA AC701 Evaluation Kit
- Price: $1,295
- Part Number: EK-A7-AC701-G
- Lead Time: 2 Weeks
- Device Support:
Product Description
The Artix®-7 FPGA AC701 Evaluation Kit features the leading system performance per watt Artix-7 family to get you quickly prototyping for your cost sensitive applications. This includes all the basic components of hardware, design tools, IP, and pre-verified reference designs. This also features a targeted reference design enabling high-performance serial connectivity and advanced memory interfacing equipped with a full license for the Northwest Logic DMA engine.
Key Features & Benefits
- Optimized for quickly prototyping cost sensitive applications using Artix-7 FPGAs
- Hardware, design tools, IP, and pre-verified reference designs
- Demonstrates a high performance data transfer system using a PCI Express® x4 Gen2
- Reference design implemented with Northwest Logic DMA engine attached to a AXI interface
- Advanced memory interface with 1GB DDR3 SODIMM up to 533MHz / 1066Mbps
- Enabling high-performance serial connectivity with GTP ports on FMC, SFP, & SMA
- Supports embedded processing with MicroBlaze, soft 32bit RISC
- Develop networking applications with 10-100-1000 Mbps Ethernet (RGMII)
- Implement Video display applications with HDMI out
- Expand I/O with the FPGA Mezzanine Card (FMC) interface
Featured Xilinx Devices
Featuring the ROHS compliant AC701 kit including the XC7A200T-2FBG676C FPGA
| Logic Cells | 215,360 |
|---|---|
| DSP Slices | 740 |
| Memory | 13,140 |
| GTP 6.6Gb/s Transceivers | 16 |
| I/O Pins | 500 |
Board Features
Featuring the Artix-7 FPGA AC701 Evaluation Kit
Clocking
- Fixed Oscillator with differential 200MHz output
- Used as the “system” clock for the FPGA
- User Programmable (IIC) Differential Oscillator (Range: 10MHz - 810 MHz, 156.250 MHz default)
- Differential SMA clock input
- Differential SMA GTP reference clock input
- Jitter attenuated clock
- Used to support CPRI/OBSAI applications that perform clock recovery from a user-supplied SFP/SFP+ module
Expansion Connectors
- FMC-HPC (Partially Populated) connector
- GTP Transceivers (x2) , 116 single-ended or 58 differential (34 LA & 24 HA) user defined signals
- VADJ can support 1.8V, 2.5V (default), or 3.3V
- PMOD (1x6 0.1" Header)
Communication & Networking
- 10/100/1000 Mbps Ethernet (RGMII)
- SFP cage
- GTP port (TX, RX) with four SMA connectors
- UART To USB Bridge
- PCI Express 4-lane edge connector
Configuration
- Onboard JTAG configuration circuitry to enable configuration over USB
- JTAG header provided for use with Xilinx download cables such as the Platform Cable USB II
- Quad SPI Flash: 32MB (256Mb)
Control & I/O
- User Push Buttons (x5)
- User DIP Switch (4-position)
- SMA User I/O (Diff Pair)
- AMS FAN Header (2 I/O)
- 7 I/O pins available through LCD header
Memory
- DDR3 SODIMM 1GB up to 533MHz / 1066Mbps
- Quad SPI Flash: 32MB (256Mb)
- IIC EEPROM: 8Kb
- SD Card Slot
Display
- HDMI video output
- LCD display (2x16)
- User LEDs (x4)
Power
- AC Power adapter (12V) or ATX
Analog
- XADC header
Featured Xilinx Devices
Featuring the ROHS compliant AC701 kit including the XC7A200T-2FBG676C FPGA
| Logic Cells | 215,360 |
|---|---|
| DSP Slices | 740 |
| Memory | 13,140 |
| GTP 6.6Gb/s Transceivers | 16 |
| I/O Pins | 500 |
What's Inside
AC701 evaluation board
Featuring the XC7A200T-2FBG676C FPGA
Full seat Vivado® Design Suite: Design Edition
Node locked & Device-locked to the Artix-7 XC7A200T FPGA, with 1 year of updates and support
Mini USB cable
HDMI cable
Micro USB cable
Power supply
Design Tools
| Name | Description | License Type |
|---|---|---|
| Vivado Design Suite: Design Edition | The Xilinx Vivado® Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for FPGAs and SoCs. | Node locked & Device-locked to the Artix-7 XC7A200T FPGA, with 1 year of updates |
Intellectual Property
| Name | Description | License Type |
|---|---|---|
| PCI Express DMA Engine (Northwest Logic) |
Northwest Logic’s PCI Express DMA Back-End Core | Hardware Time Out Evaluation license for the Northwest Logic DMA implemented with and limited to an AXI DMA Back-End interface >> See More |
| Memory Interface Generator (MIG) | MIG is a free software tool used to generate memory controllers and interfaces for Xilinx FPGAs. | No-charge IP |