Overview
The Vitis Software Platform Development Environment
The AMD Vitis™ software platform is a development environment for developing designs that includes FPGA fabric, Arm® processor subsystems, and AI Engines. The Vitis tools work in conjunction with AMD Vivado™ ML Design Suite to provide a higher level of abstraction for design development.
The Vitis software platform includes the following tools:
- Vitis Embedded – For developing C/C++ application code running on embedded Arm processors
- Compiler and simulators – For implementing designs using the AI Engine array
- Vitis HLS – For developing C/C++ based IP blocks that target FPGA fabric
- Vitis Model Composer – A model-based design tool that enables rapid design exploration within the MathWorks Simulink® environment
- A set of open-source, performance-optimized library functions, such as DSP, Vision, Solver, Ultrasound, BLAS, and many more, that can be implemented in FPGA fabric or using AI Engines
Tools & Libraries
Vitis Embedded
Vitis™ Embedded is a standalone embedded software development package for developing host applications running on embedded Arm processors.
Vitis AIE DSP Design Tools
Compilers and Simulators
AMD Versal™ adaptive SoC devices feature AI Engine arrays that enable the implementation of high-performance DSP functions in a resource- and power-optimized manner. Use of AI Engines in conjunction with the FPGA fabric resources can enable very efficient implementation of high-performance DSP applications.
Learn how to use the AMD Vitis tool flow to unlock the hardware acceleration capabilities of AI Engines for DSP applications.
Vitis HLS
The Vitis HLS tool allows users to easily create complex FPGA algorithms by synthesizing a C/C++ function into RTL.
The Vitis HLS tool is tightly integrated with both Vivado™ ML Design Suite for synthesis and place & route and the Vitis unified software platform for heterogenous system designs and applications.
Vitis Model Composer
Vitis Model Composer is a model-based design tool that enables rapid design exploration within the MathWorks Simulink® environment.
The tool also allows you to model and simulate a design with a mix of AI Engine and programmable logic (HDL/HLS) blocks.
Vitis Libraries
Open-source, performance-optimized libraries that offer out-of-the-box acceleration with minimal to zero code changes to your existing applications, written in C, C++.
Leverage the domain-specific accelerated libraries as is, modify to suit your requirements, or use as algorithmic building blocks in your custom accelerators.
Tools Uses
Different Vitis tools must be used to build different portions of AMD adaptive SoCs & FPGAs.
| FPGA (Programmable Logic) | Processing Subsystem | AI Engines |
|---|---|---|
| Vivado Design Suite / Vitis HLS / Vitis Model Composer | Vitis Embedded | AIE compilers and simulators / Vitis Model Composer |
Design Flows
Vitis Embedded Software Development Flow
(Traditionally called Embedded SDK for previous FPGA families)
Export hardware from Vivado as a platform file
Develop application code
Debug and generate boot image
Designers who are developing C/C++ code for the Arm® embedded processor subsystem in AMD adaptive SoCs will typically use this flow.
- Hardware engineers design programmable logic and export the hardware as a Xilinx Support Archive (XSA) file using AMD Vivado™ ML Design Suite.
- Software engineers incorporate this hardware design information in their target platform and use the Vitis Embedded software to develop their application code.
Developers can perform all system-level verification within the Vitis Embedded software and generate boot images to launch the application.
To learn more about the embedded software application development workflow using the Vitis software platform, refer to the Vitis tools for Embedded software development section in the User Guide (UG1400).
Vitis System Design Flow
(Hardware and Software)
System designers who are integrating both the software and hardware portions of their design in AMD adaptive SoCs will typically use this flow.
This flow is used to develop heterogenous embedded system designs comprising of software applications running on Arm® embedded processors and compute kernels running on programmable logic (PL) and/or Versal™ AI Engine arrays.
This flow comprises:
- A software host application written in C/C++ and typically run on the embedded Arm processor subsystem. It uses the native API implemented by the Xilinx Runtime Library (XRT) to interact with hardware kernels within the AMD device.
- Hardware kernels that can be generated from C++ using the AMD Vitis™ HLS tool or described directly in RTL using AMD Vivado™ ML Design Suite.
To learn more about the heterogenous system design flow using the Vitis unified software platform, refer to the Vitis Tools for Heterogenous System Design section in the user guide (UG1393).
AMD Alveo™ Data Center accelerator cards employ the same system design flow—the software program runs on an x86 host, and the kernels run in the FPGA on a PCIe®-attached acceleration card. To learn more about the data center acceleration flow using the Vitis unified software platform, refer to the Vitis tools for data center acceleration section in the user guide (UG1393).
Downloads
Visit the download page to access the new AMD Vitis™ unified software platform.
What's New
What’s New in 2023.2:
- New features for AIE-DSP designs – Enhancements to the AIE simulator and compiler
- New standalone Vitis™ Embedded installer – for designers writing embedded C code for the PS subsystem
- New Vitis Unified IDE (GUI) – Starting with 2023.2, Vitis features a new common GUI across all the Vitis tool. Vitis Unified Integrated Design Environment (IDE).
- New features for profile, debug & trace – for the AMD Versal™ AIE device family
For more details, visit our Whats New page.
