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Vitis™ Model Composer is a Model-Based Design tool that enables rapid design exploration within the MathWorks MATLAB® and Simulink® environment and accelerates the path to production on Xilinx devices through automatic code generation. You can design your DSP algorithms and iterate through them using high-level performance-optimized blocks and validate functional correctness through system-level simulations. Vitis Model Composer transforms your design to production-quality implementation through automatic optimizations. The tool provides a library of more than 200 HDL, HLS, and AI Engine blocks for the design and implementation of algorithms on Xilinx devices. It also enables importing custom HDL, HLS, and AI Engine code as blocks into the tool. Vitis Model Composer includes all the functionality of Xilinx System Generator for DSP which is no longer shipped as a standalone tool since 2021.1.
In Vitis Model Composer you can:
Create a design using optimized blocks targeting AI Engines and Programmable Logic.
Visualize and analyze simulation results and compare the output to golden references generated using MATLAB® and Simulink®.
Seamlessly co-simulate AI Engine and Programmable Logic (HLS, HDL) blocks.
Automatically generate code (AI Engines dataflow graph, RTL, HLS C++) and testbench for a design.
Import custom HLS, AI Engines, and RTL code as blocks.
Validate your design in Hardware with unparalleled Ease of Use.
Vitis Model Composer Features
Here's a quick overview of Vits™ Model Composer features. Click the other tabs for complete details.
Use MATLAB and Simulink environment to Analyze and Visualize your design:
Use optimized AI Engine, HLS, and HDL blocks directly from the Simulink library browser
Import custom AI Engines, HLS, and HDL code as blocks
Run fast simulations in Simulink environment
Compare the results with golden references in MATLAB and Simulink
Tap into intermediate signals, debug, and get visibility into the design
Co-Simulation of AI Engine and PL
Co-Simulation of AI Engine and Programmable Logic
Co-simulate a heterogeneous system:
Directly use optimized AIE/HLS/PL blocks from the library browser or import code as blocks
Seamlessly connect AI Engine blocks with HLS Kernel block
Or connect AI Engine with HDL blocks
Co-simulate AIE + PL
Increase productivity by generating code from your design:
Generate Graph code along with constraints
Generate RTL (Verilog/VHDL)
Generate optimized HLS code with inserted pragmas
Generate a test bench
Validation of Design in Hardware
Validation of Design in Hardware
Validate your design in Hardware with unparalleled Ease of Use:
Generate data movers, PS code, config file
Generate the make files needed to build a design for hardware
Move the design into hardware with a click of a button
In 2022.1, Vitis Model Composer includes many new feature additions and enhancements.
For more details, see below:
Over 50% reduction in compilation time during Simulink simulation for AI Engine DSP blocks.
Enabled streaming support for DSP library blocks.
Added the Following Blocks to DSP Library:
Stream FFT and IFFT
Stream DDS and Mixer
Dynamic Point FFT
Stream based FIR counter parts for all existing window FIR blocks (Decimators, Filters and Interpolators)
PLIO and FIFO blocks are now two separate blocks and the AIE Signal Spec block is deprecated.
You can now specify PLIO and FIFO constraints in the constraint manager.
AI Engine import blocks can now be masked as part of a bigger subsystem and their parameters can use the parameter values from the mask.
Constraint manager variables can now use the mask parameters from the subsystem mask that contains the AI Engine blocks.
HLS Kernel import block now supports template functions.
Ease of use enhancement to HLS Kernel block.
Black-box import with Vivado simulator flow is now updated to support VHDL2008 for Simulation and Code Generation by default.
New Gateway-in AXI Stream and Gateway-out AXI Stream utility blocks to facilitate connectivity between AI Engine and HDL domains.
Vitis Model Composer no longer depends on Qt libraries. This will bring a consistent look and feel to the block GUIs and improve the stability of the tool while keeping functionality the same. As a result of this update, block GUIs come up faster than Qt-based block GUIs.
HDL blocks now use Simulink native GUI instead of Qt GUI by default.
Resource analyzer is updated to use MATLAB app designer instead of Qt-based GUI.
Timing analyzer is updated to use MATLAB app designer instead of Qt-based GUI.
New SSR-FIR demo showing efficient implementations of very high data rate (over 1 Gsps) filter.
Major overhaul of the Vitis Model Composer hub block for scalability and ease of use.
System Generator Token functionality is now merged into the Vitis Model Composer hub block.
System Generator Token will be deprecated in 2022.2
Hardware validation flow now supports Linux in addition to bare-metal.
"AIE to HDL" and "HDL to AIE" blocks no longer include the HDL gateway blocks.
The product is now shipped with a snapshot of the examples for customers who do not have access to the internet. The tool will prompt the user to download a new revision of the examples from GitHub if available.
For ease of use, utility blocks that are not part of code generation are now presented with a white background color.
Enhanced and reorganized the library browser for ease of use.
Improved Support for Vector Signal Dimensions: Improvements to code generation infrastructure to handle vector [N] signals in the design, resulting in improved performance
Constant Block Enhanced for Vector Parameters: Constant block now supports interpreting vectors parameters as 1-D, similar to corresponding Constant block in Simulink library
New Example Designs with Optimized DSP Blocks
MRI Image Reconstruction with 2D-FFT
Low-pass Filter design using FIR Block
Image Smoothing filter using FIR Block
Enhancements to C/C++ Function Import: Improved error and warning messages displayed in Diagnostic Viewer, enable better troubleshooting of issues with custom code.
Customize IP Properties for IP Catalog Export Type: Specify IP Properties including name, version and hardware description language (VHDL or Verilog) for the IP packaged from the synthesized design.
Search Capabilities in Device Chooser: Quickly search for parts and boards, based on multiple criteria, using the Device Chooser dialog on the Model Composer Hub block.
FIR Block Supports Multi-Channel Processing: Enhancements to the FIR block support processing columns in the incoming signal as independent channels of data for multi-channel filtering operations.
Supported MATLAB Versions: R2018a, R2018b, R2019a and R2019b
DSP Block Library: New FFT, IFFT and FIR blocks are now available to design and implement signal processing algorithms with Model Composer
Enhancements to Throughput Control: Expanded list of blocks supported for Throughput Control. Build designs with supported blocks and control the throughput requirements of the implementation without making any structural changes to the design
Additional Blocks that Support Streaming Data : Design and Implement algorithms with high-throughput requirements using an expanded set of blocks that support operations on streaming data. Examples : Look-up Table, Delay, Matrix Multiply, Submatrix etc.
Enhanced Complex Support in C/C++ Function Import : Added support for importing functions that use hls::x_complex types as well, in addition to std::complex, expanding the support for complex signals in custom blocks.
Enhancements to C/C++ Function Import: Create custom "Source" blocks for your design using the xmcImportFunction feature
Improved Support for Row-Matrix and Column-Matrix Signal Dimensions: Improvements to the code generation infrastructure to handle Row-Matrix [Nx1] and Column-Matrix [1xN] signals in the design, resulting in improved performance.
Supported MATLAB Versions: R2018a, R2018b and R2019a