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Vitis™ Model Composer is a Model-Based Design tool that enables rapid design exploration within the MathWorks MATLAB® and Simulink® environment and accelerates the path to production on Xilinx devices through automatic code generation. You can design your DSP algorithms and iterate through them using high-level performance-optimized blocks and validate functional correctness through system-level simulations. Vitis Model Composer transforms your design to production-quality implementation through automatic optimizations. The tool provides a library of more than 200 HDL, HLS, and AI Engine blocks for the design and implementation of algorithms on Xilinx devices. It also enables importing custom HDL, HLS, and AI Engine code as blocks into the tool. Vitis Model Composer includes all the functionality of Xilinx System Generator for DSP which is no longer shipped as a standalone tool since 2021.1.
In Vitis Model Composer you can:
Create a design using optimized blocks targeting AI Engines and Programmable Logic.
Visualize and analyze simulation results and compare the output to golden references generated using MALTAB® and Simulink®.
Seamlessly co-simulate AI Engine and Programmable Logic (HLS, HDL) blocks.
Automatically generate code (AI Engines dataflow graph, RTL, HLS C++) and testbench for a design.
Import custom HLS, AI Engines, and RTL code as blocks.
Validate your design in Hardware with unparalleled Ease of Use.
Vitis Model Composer Features
Here's a quick overview of Vits™ Model Composer features. Click the other tabs for complete details.
Improved Support for Vector Signal Dimensions: Improvements to code generation infrastructure to handle vector [N] signals in the design, resulting in improved performance
Constant Block Enhanced for Vector Parameters: Constant block now supports interpreting vectors parameters as 1-D, similar to corresponding Constant block in Simulink library
New Example Designs with Optimized DSP Blocks
MRI Image Reconstruction with 2D-FFT
Low-pass Filter design using FIR Block
Image Smoothing filter using FIR Block
Enhancements to C/C++ Function Import: Improved error and warning messages displayed in Diagnostic Viewer, enable better troubleshooting of issues with custom code.
Customize IP Properties for IP Catalog Export Type: Specify IP Properties including name, version and hardware description language (VHDL or Verilog) for the IP packaged from the synthesized design.
Search Capabilities in Device Chooser: Quickly search for parts and boards, based on multiple criteria, using the Device Chooser dialog on the Model Composer Hub block.
FIR Block Supports Multi-Channel Processing: Enhancements to the FIR block support processing columns in the incoming signal as independent channels of data for multi-channel filtering operations.
Supported MATLAB Versions: R2018a, R2018b, R2019a and R2019b
DSP Block Library: New FFT, IFFT and FIR blocks are now available to design and implement signal processing algorithms with Model Composer
Enhancements to Throughput Control: Expanded list of blocks supported for Throughput Control. Build designs with supported blocks and control the throughput requirements of the implementation without making any structural changes to the design
Additional Blocks that Support Streaming Data : Design and Implement algorithms with high-throughput requirements using an expanded set of blocks that support operations on streaming data. Examples : Look-up Table, Delay, Matrix Multiply, Submatrix etc.
Enhanced Complex Support in C/C++ Function Import : Added support for importing functions that use hls::x_complex types as well, in addition to std::complex, expanding the support for complex signals in custom blocks.
Enhancements to C/C++ Function Import: Create custom "Source" blocks for your design using the xmcImportFunction feature
Improved Support for Row-Matrix and Column-Matrix Signal Dimensions: Improvements to the code generation infrastructure to handle Row-Matrix [Nx1] and Column-Matrix [1xN] signals in the design, resulting in improved performance.
Supported MATLAB Versions: R2018a, R2018b and R2019a