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Vitis Model Composer

by: Xilinx, Inc

A Xilinx toolbox for MATLAB and Simulink for DSP Design; Vitis™ Model Composer can be purchased as an add-on license to Vivado® ML Standard or Enterprise Editions and Vitis™ Development Environment.

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Overview

Vitis Model Composer Overview

Vitis™ Model Composer is a Model-Based Design tool that enables rapid design exploration within the MathWorks MATLAB® and Simulink® environment and accelerates the path to production on Xilinx devices through automatic code generation. You can design your DSP algorithms and iterate through them using high-level performance-optimized blocks and validate functional correctness through system-level simulations. Vitis Model Composer transforms your design to production-quality implementation through automatic optimizations. The tool provides a library of more than 200 HDL, HLS, and AI Engine blocks for the design and implementation of algorithms on Xilinx devices. It also enables importing custom HDL, HLS, and AI Engine code as blocks into the tool. Vitis Model Composer includes all the functionality of Xilinx System Generator for DSP which is no longer shipped as a standalone tool since 2021.1.

Featured Webinar

Model Composer Webinar

Early FPGA/SoC Design Verification with Simulink and the Vivado Simulator

Watch webinar

Vitis Model Composer Features

Here's a quick overview of Vits™ Model Composer features. Click the other tabs for complete details.

Analysis, Debugging & Visualization

Analysis, Debugging & Visualization

Use MATLAB and Simulink environment to Analyze and Visualize your design:

  • Use optimized AI Engine, HLS, and HDL blocks directly from the Simulink library browser
  • Import custom AI Engines, HLS, and HDL code as blocks
  • Run fast simulations in Simulink environment
  • Compare the results with golden references in MATLAB and Simulink
  • Tap into intermediate signals, debug, and get visibility into the design
Model Composer Analysis
Co-Simulation of AI Engine and PL

Co-Simulation of AI Engine and Programmable Logic

Co-simulate a heterogeneous system:

  • Directly use optimized AIE/HLS/PL blocks from the library browser or import code as blocks
  • Seamlessly connect AI Engine blocks with HLS Kernel block
  • Or connect AI Engine with HDL blocks
  • Co-simulate AIE + PL
Model Composer Co-Simulation
Code Generation

Code Generation

Increase productivity by generating code from your design: 

  • Generate Graph code along with constraints
  • Generate RTL (Verilog/VHDL)
  • Generate optimized HLS code with inserted pragmas
  • Generate a test bench
Model Composer Code Generation
Validation of Design in Hardware

Validation of Design in Hardware

Validate your design in Hardware with unparalleled Ease of Use:

  • Generate data movers, PS code, config file
  • Generate the make files needed to build a design for hardware
  • Move the design into hardware with a click of a button
VCK190 Board

What's New

In 2022.1, Vitis Model Composer includes many new feature additions and enhancements.

For more details, see below:

  • AI Engines
    • Over 50% reduction in compilation time during Simulink simulation for AI Engine DSP blocks.
    • Enabled streaming support for DSP library blocks.
    • Added the Following Blocks to DSP Library:
      • Stream FFT and IFFT
      • Stream DDS and Mixer
      • Dynamic Point FFT
      • FIR Resampler
      • Stream based FIR counter parts for all existing window FIR blocks (Decimators, Filters and Interpolators)
    • PLIO and FIFO blocks are now two separate blocks and the AIE Signal Spec block is deprecated.
    • You can now specify PLIO and FIFO constraints in the constraint manager.
    • AI Engine import blocks can now be masked as part of a bigger subsystem and their parameters can use the parameter values from the mask.
    • Constraint manager variables can now use the mask parameters from the subsystem mask that contains the AI Engine blocks.
  • HLS
    • HLS Kernel import block now supports template functions.
    • Ease of use enhancement to HLS Kernel block.
  • HDL
    • Black-box import with Vivado simulator flow is now updated to support VHDL2008 for Simulation and Code Generation by default.
    • New Gateway-in AXI Stream and Gateway-out AXI Stream utility blocks to facilitate connectivity between AI Engine and HDL domains.   
    • Vitis Model Composer no longer depends on Qt libraries. This will bring a consistent look and feel to the block GUIs and improve the stability of the tool while keeping functionality the same. As a result of this update, block GUIs come up faster than Qt-based block GUIs. 
      • HDL blocks now use Simulink native GUI instead of Qt GUI by default.
      • Resource analyzer is updated to use MATLAB app designer instead of Qt-based GUI.
      • Timing analyzer is updated to use MATLAB app designer instead of Qt-based GUI.
    • New SSR-FIR demo showing efficient implementations of very high data rate (over 1 Gsps) filter.
  • General
    • Major overhaul of the Vitis Model Composer hub block for scalability and ease of use. 
      • System Generator Token functionality is now merged into the Vitis Model Composer hub block.
      • System Generator Token will be deprecated in 2022.2
    • Hardware validation flow now supports Linux in addition to bare-metal. 
    • "AIE to HDL" and "HDL to AIE" blocks no longer include the HDL gateway blocks.
    • The product is now shipped with a snapshot of the examples for customers who do not have access to the internet. The tool will prompt the user to download a new revision of the examples from GitHub if available.
    • For ease of use, utility blocks that are not part of code generation are now presented with a white background color.
    • Enhanced and reorganized the library browser for ease of use. 
    • RHEL 8.x support.
    • MATLAB Support - R2021a and R2021b
tx_chain_200Mhz
200MHz TX Chain in Vitis Model Composer

View in Github 

In 2021.2, Vitis Model Composer includes many new feature additions and enhancements.

For more details, see below:

  • AI Engines
    • With a click of a button,  run a design with AI Engines and PL (HLS, HDL) blocks into a Versal AI Core hardware. 
    • Significant speed up in Simulink simulation by parallel compilation of AIE blocks.
    • Enhancements to AI Engine constraint editor
    • Addition of DDS and Mixer blocks in the AIE DSP library
    • Enhancements to "to fixed size" and "to variable size" blocks 
    • Support of int64 and uint64 data types
    • Support for accfloat and caccfloat
    • Enhancement to GitHub examples and incorporation of HLS examples in GitHub
    • Generated data flow graph code now includes PLIO specification
    • Enhanced usability to download and browse examples from GitHub
    • Support for AIE source blocks
    • xmcVitisRead and xmcVitisWrite utilities to read/write data files for AIE Simulator and/or x86Simulator
    • Systematize GUI parameters of AIE dsplib blocks
    • New 64x32 Pseudo Inverse design example
    • New Dual-Stream SSR Filter example with 64 AI Engine kernels and up to 16 GSPS throughput 
  • HDL
    • Support of Asymmetric read/write data widths for FIFO block
  • HLS
    • Supports simulation and implementation of HLS based C code that utilizes the Xilinx FIR, FFT, DDS Logicores
  • General
    • MATLAB Support - R2020a, R2020b, and R2021a
    • Newly added support for Ubuntu 20.04

Vitis Model Composer now contains the functionality of Xilinx System Generator for DSP.  Users who have been using Xilinx System Generator for DSP can continue development using Vitis Model Composer.

  • AI Engines 
    • A comprehensive constraint editor enables users to specify any constraint for AI Engine kernels in Vitis Model Composer. The generated ADF graph will contain these constraints.
    • Addition of AI Engine FFT and IFFT blocks to the library browser. 
    • Users now have access to many variations of AI Engine FIR blocks in the library browser. 
    • Ability to specify filter coefficients using input ports for FIR filters. 
    • Addition of two new utility blocks "RTP Source" and "To Variable Size".
    • Enhanced AIE Kernel import block now also supports importing templatized AI Engine functions. 
    • Ability to specify Xilinx platforms for AI Engine designs in the Hub block.
    • Through the Hub block, users can relaunch Vitis Analyzer at any time after running AIE Simulation. 
    • Users can now plot cycle approximate outputs and see estimated throughput for each output using Simulink Data Inspector. 
    • Enhanced usability to import a graph as a block using only the graph header file. 
    • Revamping of the progress bar with cancel button
    • Usability improvement during importing an AI Engine kernel or simulation of a design when MATLAB working directory and model directory are not the same. 
    • Profiling during AIE Simulation is now disabled by default. It can be optionally enabled from the Model Composer Hub block.
    • New TX Chain 200MHz example. 
    • New 2d FFT examples showcasing designs with HLS, HDL, and AI Engine blocks.
  • HDL
    • Simulation speed enhancement for SSR FIR (more than 10x improvement), and SSR FFT.
    • Simulation speed enhancement for memory blocks like RAMs, and FIFOs
    • Questa Simulator updated with VHDL 2008 in the Black-box import flow
  • General
    • Vitis Model Composer now contains the functionality of Xilinx System Generator for DSP.  Users who have been using Xilinx System Generator for DSP can continue development using Vitis Model Composer.
    • MATLAB Support - R2020a, R2020b, and R2021a

 

In 2020.2, Add-on for MATLAB & Simulink is the Unification of Xilinx Model Composer and System Generator for DSP.

Three inter-connectable domains:

  • RTL ( System Generator for DSP)
  • HLS (Model Composer)
  • AI Engine which is a new domain targetable by the Add-On for MATLAB & Simulink

AI Engine (Model Composer)

  • Imports AI Engine Kernels: C, C++, templates, state encapsulation classes
  • Imports Adaptive Dataflow Graphs: supports templates
  • Gateways between
    • AI Engine and RTL domain
    • AI Engine and HLS kernel domain
  • Accepts location constainst and FIFO insertion.
  • Library contains AI Engine DSP Library blocks
  • Runs SW Emulation and AI Engine Emulation
  • Improved Support for Vector Signal Dimensions: Improvements to code generation infrastructure to handle vector [N] signals in the design, resulting in improved performance
  • Constant Block Enhanced for Vector Parameters: Constant block now supports interpreting vectors parameters as 1-D, similar to corresponding Constant block in Simulink library
  • New Example Designs with Optimized DSP Blocks
    • MRI Image Reconstruction with 2D-FFT
    • Low-pass Filter design using FIR Block
    • Image Smoothing filter using FIR Block
  • Enhancements to C/C++ Function Import: Improved error and warning messages displayed in Diagnostic Viewer, enable better troubleshooting of issues with custom code.
  • Customize IP Properties for IP Catalog Export Type: Specify IP Properties including name, version and hardware description language (VHDL or Verilog) for the IP packaged from the synthesized design.
  • Search Capabilities in Device Chooser: Quickly search for parts and boards, based on multiple criteria, using the Device Chooser dialog on the Model Composer Hub block.
  • FIR Block Supports Multi-Channel Processing: Enhancements to the FIR block support processing columns in the incoming signal as independent channels of data for multi-channel filtering operations.
  • Supported MATLAB Versions: R2018a, R2018b, R2019a and R2019b
  • DSP Block Library: New FFT, IFFT and FIR blocks are now available to design and implement signal processing algorithms with Model Composer

  • Enhancements to Throughput Control: Expanded list of blocks supported for Throughput Control. Build designs with supported blocks and control the throughput requirements of the implementation without making any structural changes to the design

  • Additional Blocks that Support Streaming Data : Design and Implement algorithms with high-throughput requirements using an expanded set of blocks that support operations on streaming data. Examples : Look-up Table, Delay, Matrix Multiply, Submatrix etc.

  • Enhanced Complex Support in C/C++ Function Import : Added support for importing functions that use hls::x_complex types as well, in addition to std::complex, expanding the support for complex signals in custom blocks.

  • Enhancements to C/C++ Function Import: Create custom "Source" blocks for your design using the xmcImportFunction feature

  • Improved Support for Row-Matrix and Column-Matrix Signal Dimensions: Improvements to the code generation infrastructure to handle Row-Matrix [Nx1] and Column-Matrix [1xN] signals in the design, resulting in improved performance.

  • Supported MATLAB Versions: R2018a, R2018b and R2019a

Videos

Model Composer Video Link

Designing AI Engines of Xilinx Versal ACAP Using Simulink and Vitis Model Composer

Link to access video

Model Composer Video Link

Designing a FIR filter on Avnet ZUBoard using Vitis Model Composer

Link to access video

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Buy

Vitis Model Composer can be purchased as an add-on license to Vivado ML standard or enterprise editions and Vitis™ unified software platform. 

To evaluate, you can generate a free 90-day evaluation license at www.xilinx.com/getlicense.

Download

Vitis Model Composer can be additionally selected as a Design Tool and installed through Vivado Installer or Vitis installer.

Pre-Requisites

Recommended (Not Required)