Vitis™ Model Composer enables the rapid simulation, exploration, and code generation of algorithms targeted for Versal AI Engines from within the Simulink environment. You can achieve this by using the AI Engine library blocks or by importing kernels and data-flow graphs into Vitis Model Composer as blocks and controlling the behavior of the kernels and graphs by configuring the block GUI parameter. The tool also allows you to model and simulate a design with a mix of AI Engine and Programmable logic (HDL/HLS) blocks. Simulation results can be visualized by seamlessly connecting Simulink source and sink blocks with Vitis Model Composer AI Engine blocks. 

Vitis Model Composer provides a set of performance-optimized blocks for use within the Simulink environment. These include:

AI Engine blocks

• Includes a set of complex AI Engine DSP building blocks related to FIR, FFT, DDS, and mixers.
• Contains blocks to import kernels and graphs that can be targeted to the AI Engine portion of Versal devices.

HLS (Targeting PL and generates HLS code) 

• Offers predefined blocks that include functional blocks for math, linear algebra, logic, and bit-wise operations
• Block to import HLS kernels which can be targeted to the PL portion of Versal devices.

HDL (Targeting PL and generates RTL code)

• Blocks to model logic, math, and DSP elements and synthesize them on an FPGA
• Includes a FIR Compiler block that targets the dedicated DSP48E1, DSP48E2 hardware resources in Versal design
• Blocks that support connection between the AI Engine and the AMD HDL blockset.